From 4b45d4c8028026fca45f16f37896b0f24434a3d1 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Fri, 1 Apr 2022 19:01:59 +0200 Subject: [PATCH] soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree The FSP needs to program VrPowerDeliverDesign configuration per platform according to the platform capabilities to avoid incorrect electrial/power parameters. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. Signed-off-by: Lean Sheng Tan Change-Id: I74859e6735e59a15084a9e690b43f68341862833 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/chip.h | 7 +++++++ src/soc/intel/alderlake/fsp_params.c | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a69e6455ee..2dae9cd202 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -440,6 +440,13 @@ struct soc_intel_alderlake_config { */ uint8_t dmi_power_optimize_disable; + /* + * Used to communicate the power delivery design capability of the board. This + * value is an enum of the available power delivery segments that are defined in + * the Platform Design Guide. + */ + uint8_t vr_power_delivery_design; + /* * Enable(1)/Disable(0) CPU Replacement check. * Default 0. Setting this to 1 to check CPU replacement. diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd2c0bea0e..bd41480e75 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -748,6 +748,8 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, } s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; + + s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,