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northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl 

Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.

This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.

Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Furquan Shaikh 2020-06-01 13:47:28 -07:00 committed by Patrick Georgi
parent 9e94cce35d
commit 4b4c0c6016
1 changed files with 6 additions and 2 deletions
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8
src/northbridge/intel/sandybridge/acpi/hostbridge.asl
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@ -342,13 +342,17 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region // Fix up PCI memory region
// Start with Top of Lower Usable DRAM // Start with Top of Lower Usable DRAM
Local0 = ^MCHC.TLUD // Lower 20 bits of TOLUD register need to be masked since they contain lock and
// reserved bits.
Local0 = ^MCHC.TLUD & (0xfff << 20)
Local1 = ^MCHC.MEBA Local1 = ^MCHC.MEBA
// Check if ME base is equal // Check if ME base is equal
If (Local0 == Local1) { If (Local0 == Local1) {
// Use Top Of Memory instead // Use Top Of Memory instead
Local0 = ^MCHC.TOM // Lower 20 bits of TOM register need to be masked since they contain lock and
// reserved bits.
Local0 = ^MCHC.TOM & (0x7ffff << 20)
} }
PMIN = Local0 PMIN = Local0