sb/intel: Factor out soc_fill_gnvs()

Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.

Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/acpi/gnvs.c

@@ -35,6 +35,8 @@ __weak uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs_)
 	return NULL;
 }
 
+__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { }
+
 void *gnvs_get_or_create(void)
 {
 	size_t gnvs_size;

src/include/acpi/acpi_gnvs.h

@@ -34,4 +34,6 @@ void southbridge_inject_dsdt(const struct device *device);
 void acpi_create_gnvs(struct global_nvs *gnvs);
 void acpi_init_gnvs(struct global_nvs *gnvs);
 
+void soc_fill_gnvs(struct global_nvs *gnvs);
+
 #endif

src/soc/intel/broadwell/pch/lpc.c

@@ -600,18 +600,22 @@ static void pch_lpc_read_resources(struct device *dev)
 	pch_lpc_add_io_resources(dev);
 }
 
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+	/* Set unknown wake source */
+	gnvs->pm1i = -1;
+
+	/* CPU core count */
+	gnvs->pcnt = dev_count_cpu();
+}
+
 static void southcluster_inject_dsdt(const struct device *device)
 {
 	struct global_nvs *gnvs = acpi_get_gnvs();
 	if (!gnvs)
 		return;
 
-	/* Set unknown wake source */
+	soc_fill_gnvs(gnvs);
-	gnvs->pm1i = -1;
-
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	acpi_create_gnvs(gnvs);
 	acpi_inject_nvsa();
 }

src/southbridge/intel/bd82x6x/lpc.c

@@ -15,7 +15,6 @@
 #include <acpi/acpi_gnvs.h>
 #include <acpi/acpigen.h>
 #include <cpu/x86/smm.h>
-#include <cbmem.h>
 #include <string.h>
 #include "chip.h"
 #include "pch.h"
@@ -652,23 +651,23 @@ void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
 	return &gnvs->chromeos;
 }
 
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+}
+
 void southbridge_inject_dsdt(const struct device *dev)
 {
 	struct global_nvs *gnvs = acpi_get_gnvs();
+	if (!gnvs)
+		return;
 
-	if (gnvs) {
+	soc_fill_gnvs(gnvs);
+	acpi_create_gnvs(gnvs);
 
-		acpi_create_gnvs(gnvs);
+	acpi_inject_nvsa();
-
-		gnvs->apic = 1;
-		gnvs->mpen = 1; /* Enable Multi Processing */
-		gnvs->pcnt = dev_count_cpu();
-
-		/* Add it to DSDT.  */
-		acpigen_write_scope("\\");
-		acpigen_write_name_dword("NVSA", (u32) gnvs);
-		acpigen_pop_len();
-	}
 }
 
 static const char *lpc_acpi_name(const struct device *dev)

src/southbridge/intel/i82801gx/lpc.c

@@ -16,7 +16,6 @@
 #include <cpu/x86/smm.h>
 #include <acpi/acpigen.h>
 #include <arch/smp/mpspec.h>
-#include <cbmem.h>
 #include <string.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/pmbase.h>
@@ -484,23 +483,21 @@ size_t gnvs_size_of_array(void)
 	return sizeof(struct global_nvs);
 }
 
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+}
+
 void southbridge_inject_dsdt(const struct device *dev)
 {
 	struct global_nvs *gnvs = acpi_get_gnvs();
+	if (!gnvs)
+		return;
 
-	if (gnvs) {
+	soc_fill_gnvs(gnvs);
-
+	acpi_create_gnvs(gnvs);
-		gnvs->apic = 1;
+	acpi_inject_nvsa();
-		gnvs->mpen = 1; /* Enable Multi Processing */
-
-		acpi_create_gnvs(gnvs);
-
-
-		/* Add it to SSDT.  */
-		acpigen_write_scope("\\");
-		acpigen_write_name_dword("NVSA", (u32) gnvs);
-		acpigen_pop_len();
-	}
 }
 
 static const char *lpc_acpi_name(const struct device *dev)

src/southbridge/intel/ibexpeak/lpc.c

@@ -16,7 +16,6 @@
 #include <acpi/acpi_gnvs.h>
 #include <elog.h>
 #include <acpi/acpigen.h>
-#include <cbmem.h>
 #include <string.h>
 #include <cpu/x86/smm.h>
 #include "chip.h"
@@ -547,24 +546,23 @@ size_t gnvs_size_of_array(void)
 	return sizeof(struct global_nvs);
 }
 
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+}
+
 void southbridge_inject_dsdt(const struct device *dev)
 {
 	struct global_nvs *gnvs = acpi_get_gnvs();
+	if (!gnvs)
+		return;
 
-	if (gnvs) {
+	soc_fill_gnvs(gnvs);
+	acpi_create_gnvs(gnvs);
 
-		acpi_create_gnvs(gnvs);
+	acpi_inject_nvsa();
-
-		gnvs->apic = 1;
-		gnvs->mpen = 1;		/* Enable Multi Processing */
-		gnvs->pcnt = dev_count_cpu();
-
-
-		/* Add it to SSDT.  */
-		acpigen_write_scope("\\");
-		acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
-		acpigen_pop_len();
-	}
 }
 
 static const char *lpc_acpi_name(const struct device *dev)

src/southbridge/intel/lynxpoint/lpc.c

@@ -694,18 +694,22 @@ void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
 	return &gnvs->chromeos;
 }
 
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+}
+
 void southbridge_inject_dsdt(const struct device *dev)
 {
 	struct global_nvs *gnvs = acpi_get_gnvs();
 	if (!gnvs)
 		return;
 
+	soc_fill_gnvs(gnvs);
 	acpi_create_gnvs(gnvs);
 
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
-
 	acpi_inject_nvsa();
 }