mb/lenovo/x1/devicetree: Use subsystemid inheritance
Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37384 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,12 +13,10 @@ chip northbridge/intel/sandybridge
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register "gpu_pch_backlight" = "0x13121312"
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device domain 0 on
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device pci 00.0 on
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subsystemid 0x17aa 0x21e8
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end # host bridge
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device pci 02.0 on
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subsystemid 0x17aa 0x21e8
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end # vga controller
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subsystemid 0x17aa 0x21e8 inherit
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap)
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@ -26,37 +24,23 @@ chip northbridge/intel/sandybridge
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# X1 does not have ExpressCard slot
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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device pci 1a.0 on
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subsystemid 0x17aa 0x21e8
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end # USB2 EHCI #2
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device pci 1b.0 on
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subsystemid 0x17aa 0x21e8
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end # High Definition Audio
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.1 on
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subsystemid 0x17aa 0x21e8
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end # PCIe Port #2 (wlan)
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device pci 1c.1 on end # PCIe Port #2 (wlan)
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 on
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subsystemid 0x17aa 0x21e8
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chip drivers/ricoh/rce822 # Ricoh cardreader
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device pci 00.0 on
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subsystemid 0x17aa 0x21e8
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end
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device pci 00.0 on end
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end
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end # PCIe Port #5 (SD)
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on
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subsystemid 0x17aa 0x21e8
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end # PCIe Port #7
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device pci 1c.6 on end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on
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subsystemid 0x17aa 0x21e8
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end # USB2 EHCI #1
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on #LPC bridge
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subsystemid 0x17aa 0x21e8
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chip ec/lenovo/h8
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register "config2" = "0xe0"
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register "config3" = "0xc0"
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@ -71,15 +55,9 @@ chip northbridge/intel/sandybridge
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register "has_bdc_detection" = "0"
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end
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end # LPC bridge
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device pci 1f.2 on
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subsystemid 0x17aa 0x21e8
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end # SATA Controller 1
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device pci 1f.3 on
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subsystemid 0x17aa 0x21e8
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end # SMBus
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device pci 1f.6 on
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subsystemid 0x17aa 0x21e8
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end # Thermal
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.6 on end # Thermal
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end
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end
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end
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