From 4b5a490b6f3faffe1880c731b50d1a4adabfb622 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 19 Nov 2021 11:38:35 -0700 Subject: [PATCH] src/cpu,soc/amd/common/block/cpu: Add preload_microcode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will enable preloading the microcode. By preloading the file, into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush with CL chain and see microcode preloading and a reduction of 1 ms. | 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) | | 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) | Signed-off-by: Raul E Rangel Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/cpu/Makefile.inc | 5 +++++ src/include/cpu/amd/microcode.h | 1 + src/soc/amd/common/block/cpu/update_microcode.c | 16 ++++++++++++++-- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index ec2f19fd18..9f1e6c4bf5 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -56,7 +56,12 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +cpu_microcode_blob.bin-align := 64 +else cpu_microcode_blob.bin-align := 16 +endif ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index 800661b797..74075944bb 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -2,5 +2,6 @@ #define CPU_AMD_MICROCODE_H void amd_update_microcode_from_cbfs(void); +void preload_microcode(void); #endif /* CPU_AMD_MICROCODE_H */ diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index e6a57f5c99..33b244d192 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -10,6 +10,8 @@ #include #include +#define CPU_MICROCODE_BLOB_NAME "cpu_microcode_blob.bin" + _Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0, "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set"); @@ -97,9 +99,10 @@ void amd_update_microcode_from_cbfs(void) /* Cache the buffer so each CPU doesn't need to read the uCode from flash */ if (!cache_valid) { timestamp_add_now(TS_READ_UCODE_START); - ucode_list = cbfs_map("cpu_microcode_blob.bin", &ucode_len); + ucode_list = cbfs_map(CPU_MICROCODE_BLOB_NAME, &ucode_len); if (!ucode_list) { - printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); + printk(BIOS_WARNING, + CPU_MICROCODE_BLOB_NAME " not found. Skipping updates.\n"); return; } @@ -120,3 +123,12 @@ void amd_update_microcode_from_cbfs(void) apply_microcode_patch(&ucode_cache); } + +void preload_microcode(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading microcode %s\n", CPU_MICROCODE_BLOB_NAME); + cbfs_preload(CPU_MICROCODE_BLOB_NAME); +}