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mb/google/brya/var/volmar: Disable PCH USB2 phy power gating 

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.

BUG=None
TEST=Verify the build for volmar board

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Ren Kuo 2022-06-22 16:08:40 +08:00 committed by Martin L Roth
parent 68033c2483
commit 4b5a98d8d5
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/brya/variants/volmar/overridetree.cb
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@ -23,6 +23,10 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
# As per Intel Advisory doc#723158, the change is required to prevent possible
# display flickering issue.
register "usb2_phy_sus_pg_disable" = "1"
register "tcss_aux_ori" = "1" register "tcss_aux_ori" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"