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mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region 

Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to
decompress and load more data from CBFS in romstage.

BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tristan Shieh 2019-08-16 15:35:50 +08:00 committed by Patrick Georgi
parent 526d840b13
commit 4b5eefa675
1 changed files with 5 additions and 5 deletions
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10
src/soc/mediatek/mt8183/include/soc/memlayout.ld
View File

@ -32,11 +32,11 @@ SECTIONS
VBOOT2_TPM_LOG(0x00103000, 2K) VBOOT2_TPM_LOG(0x00103000, 2K)
PRERAM_CBMEM_CONSOLE(0x00103800, 14K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K)
WATCHDOG_TOMBSTONE(0x00107000, 4) WATCHDOG_TOMBSTONE(0x00107000, 4)
PRERAM_CBFS_CACHE(0x00107004, 16K - 4) PRERAM_CBFS_CACHE(0x00107004, 48K - 4)
TIMESTAMP(0x0010B000, 4K) TIMESTAMP(0x00113000, 4K)
STACK(0x0010C000, 16K) STACK(0x00114000, 16K)
TTB(0x00110000, 28K) TTB(0x00118000, 28K)
DMA_COHERENT(0x00117000, 4K) DMA_COHERENT(0x0011f000, 4K)
SRAM_END(0x00120000) SRAM_END(0x00120000)
SRAM_L2C_START(0x00200000) SRAM_L2C_START(0x00200000)