intel/sklrvp: Remove mainboard
The Intel Skylake RVP3 mainboard is not building, and according to Intel, there is no plan to continue working on it for coreboot. The intel/kunimitsu board is the Skylake reference design for coreboot.org. Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13469 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Martin Roth
parent
393d9322ba
commit
4b7a00867a
|
|
@ -1,44 +0,0 @@
|
|||
if BOARD_INTEL_SKLRVP
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_SMI_HANDLER
|
||||
select MAINBOARD_HAS_CHROMEOS
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
select MMCONF_SUPPORT
|
||||
select MONOTONIC_TIMER_MSR
|
||||
select PCIEXP_L1_SUB_STATE
|
||||
select SOC_INTEL_SKYLAKE
|
||||
|
||||
config CHROMEOS
|
||||
select LID_SWITCH
|
||||
select CHROMEOS_RAMOOPS_DYNAMIC
|
||||
select CHROMEOS_VBNV_CMOS
|
||||
select VBOOT_DYNAMIC_WORK_BUFFER
|
||||
select VIRTUAL_DEV_SWITCH
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 18
|
||||
|
||||
config BOOT_MEDIA_SPI_BUS
|
||||
int
|
||||
default 0
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default "intel/sklrvp"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "Skylake RVP"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 8
|
||||
|
||||
endif
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_INTEL_SKLRVP
|
||||
bool "Skylake RVP3"
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2013 Google Inc.
|
||||
## Copyright (C) 2015 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
subdirs-y += spd
|
||||
|
||||
romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
|
||||
romstage-y += pei_data.c
|
||||
|
||||
ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
|
||||
ramstage-y += pei_data.c
|
||||
ramstage-y += ramstage.c
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Successful builds for this board require the Skylake FSP binary and header files
|
||||
along with the Skylake microcode files from Intel.
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Name (OIPG, Package() {
|
||||
Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button
|
||||
Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect
|
||||
})
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <mainboard/intel/sklrvp/onboard.h>
|
||||
|
||||
/*
|
||||
* LPC Trusted Platform Module
|
||||
*/
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/tpm/acpi/tpm.asl>
|
||||
}
|
||||
|
||||
/*
|
||||
* WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
|
||||
*/
|
||||
Scope (\_SB.PCI0.RP01)
|
||||
{
|
||||
Device (WLAN)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
|
||||
/* GPIO10 is PCH_WLAN_WAKE_L */
|
||||
Name (GPIO, 10)
|
||||
|
||||
Name (_PRW, Package() { GPIO, 3 })
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C0)
|
||||
{
|
||||
Device (ETPA)
|
||||
{
|
||||
Name (_HID, "SYN2393")
|
||||
Name (_CID, "PNP0C50")
|
||||
Name (_DDN, "Synaptic Touchpad")
|
||||
Name (_UID, 3)
|
||||
Name (ISTP, 1) /* Touchpad */
|
||||
|
||||
/* Fetch HidDescriptorAddress, Register offset in the
|
||||
* I2C device at which the HID descriptor can be read
|
||||
*/
|
||||
Method (_DSM, 4, NotSerialized)
|
||||
{
|
||||
If (LEqual (Arg0, ToUUID (
|
||||
"3cdff6f7-4267-4555-ad05-b30a3d8938de")))
|
||||
{
|
||||
If (LEqual (Arg2, Zero))
|
||||
{
|
||||
If (LEqual (Arg1, One))
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x03
|
||||
})
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x00
|
||||
})
|
||||
}
|
||||
}
|
||||
If (LEqual (Arg2, One))
|
||||
{
|
||||
Return (0x20)
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x00
|
||||
})
|
||||
}
|
||||
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_TOUCHPAD_I2C_ADDR, /* SlaveAddress */
|
||||
ControllerInitiated, /* SlaveMode */
|
||||
400000, /* ConnectionSpeed */
|
||||
AddressingMode7Bit, /* AddressingMode */
|
||||
"\\_SB.PCI0.I2C0", /* ResourceSource */
|
||||
)
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow)
|
||||
{ BOARD_TOUCHPAD_IRQ }
|
||||
})
|
||||
}
|
||||
|
||||
//-----------------------------------
|
||||
// HD Audio I2S Codec device
|
||||
// Realtek ALC286S (I2SC = 2)
|
||||
//-----------------------------------
|
||||
Device (HDAC)
|
||||
{
|
||||
Name (_HID, "INT343A")
|
||||
Name (_CID, "INT343A")
|
||||
Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
|
||||
Name (_UID, 1)
|
||||
|
||||
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
|
||||
{
|
||||
/* update Audio codec slave address in runtime */
|
||||
Name (RBUF, ResourceTemplate ()
|
||||
{
|
||||
I2cSerialBus (0x1C, ControllerInitiated, 400000,
|
||||
AddressingMode7Bit, "\\_SB.PCI0.I2C0",
|
||||
0x00, ResourceConsumer, ,)
|
||||
})
|
||||
|
||||
/* update interrupt number in runtime */
|
||||
Name (SBFI, ResourceTemplate ()
|
||||
{
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow,
|
||||
ExclusiveAndWake)
|
||||
{
|
||||
GPP_E22_IRQ
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF) /* I2S Codec Enabled */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C1)
|
||||
{
|
||||
Device (ATSA)
|
||||
{
|
||||
Name (_HID, "ATML3432")
|
||||
Name (_DDN, "Atmel Touchscreen")
|
||||
Name (_UID, 5)
|
||||
Name (_S0W, 4)
|
||||
Name (ISTP, 0) /* TouchScreen */
|
||||
Name (_CID, "PNP0C50")
|
||||
|
||||
/* Fetch HidDescriptorAddress, Register offset in the
|
||||
* I2C device at which the HID descriptor can be read
|
||||
*/
|
||||
Method (_DSM, 4, NotSerialized)
|
||||
{
|
||||
If (LEqual (Arg0, ToUUID (
|
||||
"3cdff6f7-4267-4555-ad05-b30a3d8938de")))
|
||||
{
|
||||
If (LEqual (Arg2, Zero))
|
||||
{
|
||||
If (LEqual (Arg1, One))
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x03
|
||||
})
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x00
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
If (LEqual (Arg2, One))
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x00
|
||||
})
|
||||
}
|
||||
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress
|
||||
ControllerInitiated, // SlaveMode
|
||||
400000, // ConnectionSpeed
|
||||
AddressingMode7Bit, // AddressingMode
|
||||
"\\_SB.PCI0.I2C1", // ResourceSource
|
||||
)
|
||||
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow)
|
||||
{ BOARD_TOUCHSCREEN_IRQ }
|
||||
})
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
Category: eval
|
||||
Release year: 2015
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <rules.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <string.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
#if ENV_RAMSTAGE
|
||||
#include <boot/coreboot_tables.h>
|
||||
|
||||
#define GPIO_COUNT 6
|
||||
|
||||
void fill_lb_gpios(struct lb_gpios *gpios)
|
||||
{
|
||||
struct lb_gpio *gpio;
|
||||
|
||||
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
|
||||
gpios->count = GPIO_COUNT;
|
||||
|
||||
gpio = gpios->gpios;
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
|
||||
get_recovery_mode_switch());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
|
||||
get_developer_mode_switch());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid",
|
||||
get_lid_switch());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
|
||||
}
|
||||
#endif /* ENV_RAMSTAGE */
|
||||
|
||||
int get_lid_switch(void)
|
||||
{
|
||||
/* Default to force open */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* The dev-switch is virtual */
|
||||
int get_developer_mode_switch(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_recovery_mode_switch(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_write_protect_state(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
FLASH@0xff000000 0x1000000 {
|
||||
SI_ALL@0x0 0xa00000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_ME@0x1000 0x1ff000
|
||||
}
|
||||
SI_BIOS@0xa00000 0x600000 {
|
||||
RW_SECTION_A@0x0 0x100000 {
|
||||
VBLOCK_A@0x0 0x10000
|
||||
FW_MAIN_A(CBFS)@0x10000 0xeffc0
|
||||
RW_FWID_A@0xfffc0 0x40
|
||||
}
|
||||
RW_SECTION_B@0x100000 0x100000 {
|
||||
VBLOCK_B@0x0 0x10000
|
||||
FW_MAIN_B(CBFS)@0x10000 0xeffc0
|
||||
RW_FWID_B@0xfffc0 0x40
|
||||
}
|
||||
RW_MRC_CACHE@0x200000 0x10000
|
||||
RW_ELOG@0x210000 0x4000
|
||||
RW_SHARED@0x214000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD@0x218000 0x2000
|
||||
RW_UNUSED@0x21a000 0x6000
|
||||
WP_RO@0x300000 0x300000 {
|
||||
RO_VPD@0x0 0x4000
|
||||
RO_UNUSED@0x4000 0xc000
|
||||
RO_SECTION@0x10000 0x1f0000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_FRID@0x800 0x40
|
||||
RO_FRID_PAD@0x840 0x7c0
|
||||
GBB@0x1000 0xef000
|
||||
COREBOOT(CBFS)@0xf0000 0x200000
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,135 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
## Copyright (C) 2015 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 r 0 reboot_bits
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
#411 5 r 0 unused
|
||||
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
#544 440 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
||||
|
||||
|
|
@ -1,142 +0,0 @@
|
|||
chip soc/intel/skylake
|
||||
|
||||
# SerialIO device modes
|
||||
register "SerialIoDevMode" = "{ \
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexSpi0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexSpi1] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexUart0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart2] = PchSerialIoPci, \
|
||||
}"
|
||||
|
||||
# Enable eDP Hotplug with 6ms pulse
|
||||
register "gpu_dp_d_hotplug" = "0x06"
|
||||
|
||||
# Enable DDI1 Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
# Enable DDI2 Hotplug with 6ms pulse
|
||||
register "gpu_dp_c_hotplug" = "0x06"
|
||||
|
||||
# Set backlight PWM values for eDP
|
||||
register "gpu_cpu_backlight" = "0x00000200"
|
||||
register "gpu_pch_backlight" = "0x04000000"
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
register "gpu_panel_power_cycle_delay" = "6" # 500ms
|
||||
register "gpu_panel_power_up_delay" = "2000" # 200ms
|
||||
register "gpu_panel_power_down_delay" = "500" # 50ms
|
||||
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
|
||||
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
|
||||
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "0"
|
||||
|
||||
# Probeless Trace function
|
||||
register "ProbelessTrace" = "0"
|
||||
|
||||
# Lan
|
||||
register "EnableLan" = "0"
|
||||
|
||||
# SATA related
|
||||
register "EnableSata" = "0"
|
||||
register "SataSalpSupport" = "0"
|
||||
register "SataMode" = "0"
|
||||
register "SataPortsEnable[0]" = "0"
|
||||
|
||||
# Audio related
|
||||
register "EnableAzalia" = "1"
|
||||
register "EnableTraceHub" = "0"
|
||||
register "DspEnable" = "1"
|
||||
|
||||
# I/O Buffer Ownership:
|
||||
# 0: HD-A Link
|
||||
# 1 Shared, HD-A Link and I2S Port
|
||||
# 3: I2S Ports
|
||||
register "IoBufferOwnership" = "3"
|
||||
|
||||
# USB related
|
||||
register "SsicPortEnable" = "0"
|
||||
|
||||
# SMBUS
|
||||
register "SmbusEnable" = "1"
|
||||
|
||||
# Camera
|
||||
register "Cio2Enable" = "0"
|
||||
|
||||
# eMMC
|
||||
register "ScsEmmcEnabled" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "0"
|
||||
register "ScsSdCardEnabled" = "2"
|
||||
|
||||
# Integrated Sensor
|
||||
register "IshEnable" = "0"
|
||||
|
||||
# XDCI controller
|
||||
register "XdciEnable" = "0"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Thermal Subsystem
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 on end # I2C #2
|
||||
device pci 15.3 on end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT-Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # UART #2
|
||||
device pci 19.1 on end # I2C #5
|
||||
device pci 19.2 on end # I2C #4
|
||||
device pci 1c.0 off end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 off end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 on end # UART #1
|
||||
device pci 1e.2 on end # GSPI #0
|
||||
device pci 1e.3 on end # GSPI #1
|
||||
device pci 1e.4 on end # eMMC
|
||||
device pci 1e.5 off end # SDIO
|
||||
device pci 1e.6 on end # SDCard
|
||||
device pci 1f.0 on end # LPC Interface
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 off end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include <soc/intel/skylake/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/skylake/acpi/globalnvs.asl>
|
||||
|
||||
// CPU
|
||||
#include <soc/intel/skylake/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/skylake/acpi/systemagent.asl>
|
||||
#include <soc/intel/skylake/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
// Chipset specific sleep states
|
||||
#include <soc/intel/skylake/acpi/sleepstates.asl>
|
||||
|
||||
// Mainboard specific
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <soc/acpi.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 5;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
acpi_fill_in_fadt(fadt);
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
|
|
@ -1,351 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef _GPIORVP3_H_
|
||||
#define _GPIORVP3_H_
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const GPIO_INIT_CONFIG GpioTableRvp3[] = {
|
||||
{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntEdge | GpioIntSci, GpioResetDeep,
|
||||
GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal,
|
||||
GpioTermWpu20K}},
|
||||
{GPIO_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntEdge | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut,
|
||||
GpioOutLow, GpioIntLevel | GpioIntDis, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
|
||||
{GPIO_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,
|
||||
GpioTolerance1v8 | GpioTermNone}},
|
||||
{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}},
|
||||
{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{GPIO_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetPwrGood,
|
||||
GpioTermNone}},
|
||||
{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermWpu20K}},
|
||||
{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{GPIO_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
/*
|
||||
* Gpio based irq for touchpad, 18th index in North Bank
|
||||
* MAX_DIRECT_IRQ + GPSW_SIZE + 19
|
||||
*/
|
||||
#define SKLRVP_TOUCHPAD_IRQ 33
|
||||
|
||||
#define SKLRVP_TOUCH_IRQ 31
|
||||
|
||||
#define BOARD_TOUCHPAD_NAME "touchpad"
|
||||
#define BOARD_TOUCHPAD_IRQ SKLRVP_TOUCHPAD_IRQ
|
||||
#define BOARD_TOUCHPAD_I2C_BUS 0
|
||||
#define BOARD_TOUCHPAD_I2C_ADDR 0x20
|
||||
|
||||
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
|
||||
#define BOARD_TOUCHSCREEN_IRQ SKLRVP_TOUCH_IRQ
|
||||
#define BOARD_TOUCHSCREEN_I2C_BUS 0
|
||||
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
|
||||
|
||||
#endif
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||
{
|
||||
|
||||
/* DQ byte map for sklrvp board */
|
||||
const u8 dq_map[2][12] = {
|
||||
{0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
|
||||
0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
|
||||
{0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC ,
|
||||
0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
|
||||
/* DQS CPU<>DRAM map for sklrvp board */
|
||||
const u8 dqs_map[2][8] = {
|
||||
{0, 1, 3, 2, 4, 5, 6, 7},
|
||||
{1, 0, 4, 5, 2, 3, 6, 7} };
|
||||
|
||||
/* Rcomp resistor*/
|
||||
const u16 RcompResistor[3] = {200, 81, 162 };
|
||||
|
||||
/* Rcomp target*/
|
||||
const u16 RcompTarget[5] = {100, 40, 40, 23, 40};
|
||||
|
||||
pei_data->ec_present = 1;
|
||||
|
||||
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
||||
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
||||
memcpy(pei_data->RcompResistor, RcompResistor,
|
||||
sizeof(RcompResistor));
|
||||
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||
sizeof(RcompTarget));
|
||||
}
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "gpio_rvp3.h"
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
|
||||
{
|
||||
/*update gpio table*/
|
||||
params->GpioTablePtr = (UINT32 *)GpioTableRvp3;
|
||||
}
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/cpu.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/romstage.h>
|
||||
#include "spd/spd.h"
|
||||
|
||||
void mainboard_romstage_entry(struct romstage_params *params)
|
||||
{
|
||||
post_code(0x31);
|
||||
/* Fill out PEI DATA */
|
||||
mainboard_fill_pei_data(params->pei_data);
|
||||
mainboard_fill_spd_data(params->pei_data);
|
||||
/* Initliaze memory */
|
||||
romstage_common(params);
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(
|
||||
struct romstage_params *params,
|
||||
MEMORY_INIT_UPD *memory_params)
|
||||
{
|
||||
/* Get SPD data passing strucutre and initialize it.*/
|
||||
if (params->pei_data->spd_data[0][0][0] != 0) {
|
||||
memory_params->MemorySpdPtr00 =
|
||||
(UINT32)(params->pei_data->spd_data[0][0]);
|
||||
memory_params->MemorySpdPtr10 =
|
||||
(UINT32)(params->pei_data->spd_data[1][0]);
|
||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
|
||||
memory_params->MemorySpdPtr00);
|
||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
|
||||
memory_params->MemorySpdPtr01);
|
||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
|
||||
memory_params->MemorySpdPtr10);
|
||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
|
||||
memory_params->MemorySpdPtr11);
|
||||
}
|
||||
/*
|
||||
* Configure the DQ/DQS settings if required. In general the settings
|
||||
* should be set in the FSP flash image and should not need to be
|
||||
* changed.
|
||||
*/
|
||||
memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
|
||||
sizeof(params->pei_data->dq_map[0]));
|
||||
memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
|
||||
sizeof(params->pei_data->dq_map[1]));
|
||||
memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
|
||||
sizeof(params->pei_data->dqs_map[0]));
|
||||
memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
|
||||
sizeof(params->pei_data->dqs_map[1]));
|
||||
memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
|
||||
sizeof(params->pei_data->RcompResistor));
|
||||
memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
|
||||
sizeof(params->pei_data->RcompTarget));
|
||||
|
||||
/* update spd length*/
|
||||
memory_params->MemorySpdDataLen = SPD_LEN;
|
||||
memory_params->DqPinsInterleaved = FALSE;
|
||||
}
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2014 Google Inc.
|
||||
## Copyright (C) 2015 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
romstage-y += spd.c
|
||||
|
||||
SPD_BIN = $(obj)/spd.bin
|
||||
|
||||
# SPD data by index. No method for board identification yet
|
||||
SPD_SOURCES = rvp3 # 0
|
||||
SPD_SOURCES += empty # 1
|
||||
|
||||
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
|
||||
|
||||
# Include spd rom data
|
||||
$(SPD_BIN): $(SPD_DEPS)
|
||||
for f in $+; \
|
||||
do for c in $$(cat $$f | grep -v ^#); \
|
||||
do printf $$(printf '\%o' 0x$$c); \
|
||||
done; \
|
||||
done > $@
|
||||
|
||||
cbfs-files-y += spd.bin
|
||||
spd.bin-file := $(SPD_BIN)
|
||||
spd.bin-type := spd
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01
|
||||
78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
|
||||
00 00 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 55 00 00 00 00 00
|
||||
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
|
||||
20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/byteorder.h>
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <mainboard/intel/sklrvp/spd/spd.h>
|
||||
|
||||
static void mainboard_print_spd_info(uint8_t spd[])
|
||||
{
|
||||
const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
|
||||
const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
|
||||
const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
|
||||
const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
|
||||
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
|
||||
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
|
||||
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
|
||||
char spd_name[SPD_PART_LEN+1] = { 0 };
|
||||
|
||||
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
|
||||
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
|
||||
int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
|
||||
int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
|
||||
int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
|
||||
int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
|
||||
int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
|
||||
|
||||
/* Module type */
|
||||
printk(BIOS_INFO, "SPD: module type is ");
|
||||
switch (spd[SPD_DRAM_TYPE]) {
|
||||
case SPD_DRAM_DDR3:
|
||||
printk(BIOS_INFO, "DDR3\n");
|
||||
break;
|
||||
case SPD_DRAM_LPDDR3:
|
||||
printk(BIOS_INFO, "LPDDR3\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Module Part Number */
|
||||
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
|
||||
spd_name[SPD_PART_LEN] = 0;
|
||||
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
|
||||
|
||||
printk(BIOS_INFO,
|
||||
"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
|
||||
banks, ranks, rows, cols, capmb);
|
||||
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
|
||||
devw, busw);
|
||||
|
||||
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
|
||||
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
|
||||
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
|
||||
capmb / 8 * busw / devw * ranks);
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data)
|
||||
{
|
||||
char *spd_file;
|
||||
size_t spd_file_len;
|
||||
int spd_index;
|
||||
|
||||
/* Find the SPD data in CBFS. */
|
||||
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
|
||||
&spd_file_len);
|
||||
if (!spd_file)
|
||||
die("SPD data not found.");
|
||||
|
||||
/* make sure we have at least one SPD in the file. */
|
||||
if (spd_file_len < SPD_LEN)
|
||||
die("Missing SPD data.");
|
||||
|
||||
/* Add board SKU detection here. Currently we only support one. */
|
||||
spd_index = 0;
|
||||
|
||||
/* Make sure we did not overrun the buffer */
|
||||
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
|
||||
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
|
||||
spd_index = 0;
|
||||
}
|
||||
|
||||
/* Assume same memory in both channels */
|
||||
spd_index *= SPD_LEN;
|
||||
memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
|
||||
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
|
||||
|
||||
/* Make sure a valid SPD was found */
|
||||
if (pei_data->spd_data[0][0][0] == 0)
|
||||
die("Invalid SPD data.");
|
||||
|
||||
mainboard_print_spd_info(pei_data->spd_data[0][0]);
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MAINBOARD_SPD_H_
|
||||
#define _MAINBOARD_SPD_H_
|
||||
|
||||
#define SPD_LEN 256
|
||||
|
||||
#define SPD_DRAM_TYPE 2
|
||||
#define SPD_DRAM_DDR3 0x0b
|
||||
#define SPD_DRAM_LPDDR3 0xf1
|
||||
#define SPD_DENSITY_BANKS 4
|
||||
#define SPD_ADDRESSING 5
|
||||
#define SPD_ORGANIZATION 7
|
||||
#define SPD_BUS_DEV_WIDTH 8
|
||||
#define SPD_PART_OFF 128
|
||||
#define SPD_PART_LEN 18
|
||||
|
||||
|
||||
#endif /* _MAINBOARD_SPD_H_ */
|
||||
Loading…
Reference in New Issue