GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/intel: Drop unneeded empty lines 

Change-Id: I3fdc521d30155c4275c336afe03244311f584e71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-09-10 11:34:01 +02:00 committed by Michael Niewöhner
parent 3ff7bcf10e
commit 4b7f3151a8
21 changed files with 0 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/intel/baskingridge/acpi_tables.c
View File

@ -25,7 +25,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* TPM Present */ /* TPM Present */
gnvs->tpmp = 1; gnvs->tpmp = 1;
#if CONFIG(CHROMEOS) #if CONFIG(CHROMEOS)
/* Emerald Lake has no EC (?) */ /* Emerald Lake has no EC (?) */
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;

2
src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
View File

@ -280,8 +280,6 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)

1
src/mainboard/intel/cedarisland_crb/dsdt.asl
View File

@ -26,7 +26,6 @@ DefinitionBlock(
} }
Device (UNC0) Device (UNC0)
{ {
Name (_HID, EisaId ("PNP0A03")) Name (_HID, EisaId ("PNP0A03"))

2
src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
View File

@ -579,8 +579,6 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)

1
src/mainboard/intel/d945gclf/acpi/superio.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
Device (SIO1) Device (SIO1)
{ {
Name (_HID, EISAID("PNP0A05")) Name (_HID, EISAID("PNP0A05"))

2
src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
View File

@ -86,8 +86,6 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP),
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
}; };
const struct pad_config *variant_gpio_table(size_t *num) const struct pad_config *variant_gpio_table(size_t *num)

2
src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
View File

@ -86,8 +86,6 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP),
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
}; };
const struct pad_config *variant_gpio_table(size_t *num) const struct pad_config *variant_gpio_table(size_t *num)

1
src/mainboard/intel/jasperlake_rvp/board_id.h
View File

@ -3,7 +3,6 @@
#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_
#define _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_
/* Board/FAB ID Command */ /* Board/FAB ID Command */
#define EC_FAB_ID_CMD 0x0D #define EC_FAB_ID_CMD 0x0D

2
src/mainboard/intel/kblrvp/acpi/dptf.asl
View File

@ -8,8 +8,6 @@
#define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC3 60
#define DPTF_CPU_ACTIVE_AC4 50 #define DPTF_CPU_ACTIVE_AC4 50
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },

1
src/mainboard/intel/kblrvp/romstage.c
View File

@ -10,7 +10,6 @@
#include <spd_bin.h> #include <spd_bin.h>
#include "board_id.h" #include "board_id.h"
void mainboard_memory_init_params(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd)
{ {
FSP_M_CONFIG *mem_cfg; FSP_M_CONFIG *mem_cfg;

2
src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
View File

@ -17,7 +17,6 @@
#define IO_EXPANDER_P2DOUT 0x06 #define IO_EXPANDER_P2DOUT 0x06
#define IO_EXPANDER_1_ADDR 0x23 #define IO_EXPANDER_1_ADDR 0x23
/* GPE_EC_WAKE */ /* GPE_EC_WAKE */
#define GPE_EC_WAKE GPE0_LAN_WAK #define GPE_EC_WAKE GPE0_LAN_WAK
@ -200,7 +199,6 @@ static const struct pad_config early_gpio_table[] = {
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
}; };
#endif #endif
#endif #endif

1
src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
View File

@ -165,6 +165,5 @@ static const struct pad_config early_gpio_table[] = {
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
}; };
#endif #endif
#endif #endif

1
src/mainboard/intel/kunimitsu/mainboard.c
View File

@ -44,7 +44,6 @@ static unsigned long mainboard_write_acpi_tables(
if (nhlt_soc_add_dmic_array(nhlt, 2)) if (nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
/* 4 Channel DMIC array. */ /* 4 Channel DMIC array. */
if (nhlt_soc_add_dmic_array(nhlt, 4)) if (nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");

1
src/mainboard/intel/kunimitsu/spd/spd_util.c
View File

@ -49,7 +49,6 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
static const u16 StrengthendRcompTarget[5] = { static const u16 StrengthendRcompTarget[5] = {
100, 40, 40, 21, 40 }; 100, 40, 40, 21, 40 };
if (mem_cfg_id == K4E6E304EE_MEM_ID) { if (mem_cfg_id == K4E6E304EE_MEM_ID) {
memcpy(rcomp_strength_ptr, StrengthendRcompTarget, memcpy(rcomp_strength_ptr, StrengthendRcompTarget,
sizeof(StrengthendRcompTarget)); sizeof(StrengthendRcompTarget));

1
src/mainboard/intel/saddlebrook/romstage.c
View File

@ -8,7 +8,6 @@
#include "spd/spd.h" #include "spd/spd.h"
#include <spd_bin.h> #include <spd_bin.h>
void mainboard_memory_init_params(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd)
{ {
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;

2
src/mainboard/intel/strago/acpi/dptf.asl
View File

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 75 #define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_PASSIVE 65
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_PASSIVE 49
#define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR2_CRITICAL 75
#define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */ /* Charger performance states, board-specific values from charger and EC */

2
src/mainboard/intel/strago/com_init.c
View File

@ -12,8 +12,6 @@
* by pad number and which community it is in. * by pad number and which community it is in.
*/ */
/* family number in high byte and inner pad number in lowest byte */ /* family number in high byte and inner pad number in lowest byte */
void bootblock_mainboard_early_init(void) void bootblock_mainboard_early_init(void)

4
src/mainboard/intel/strago/gpio.c
View File

@ -68,7 +68,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END GPIO_END
}; };
/* South West Community */ /* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = { static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */ GPIO_NC, /* 00 FST_SPI_D2 */
@ -135,7 +134,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END GPIO_END
}; };
/* North Community */ /* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = { static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */ GPIO_NC, /* 00 GPIO_DFX0 */
@ -205,7 +203,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END GPIO_END
}; };
/* East Community */ /* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = { static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */ Native_M1, /* 00 PMU_SLP_S3_B */
@ -235,7 +232,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END GPIO_END
}; };
static struct soc_gpio_config gpio_config = { static struct soc_gpio_config gpio_config = {
/* BSW */ /* BSW */
.north = gpn_gpio_map, .north = gpn_gpio_map,

1
src/mainboard/intel/strago/mainboard.c
View File

@ -20,7 +20,6 @@ static void mainboard_enable(struct device *dev)
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };

3
src/mainboard/intel/strago/onboard.h
View File

@ -25,7 +25,6 @@
#define BOARD_TOUCH_IRQ 184 #define BOARD_TOUCH_IRQ 184
/* Audio: Gpio index in SW bank */ /* Audio: Gpio index in SW bank */
#define JACK_DETECT_GPIO_INDEX 95 #define JACK_DETECT_GPIO_INDEX 95
/* SCI: Gpio index in N bank */ /* SCI: Gpio index in N bank */
@ -43,8 +42,6 @@
#define BOARD_TOUCHSCREEN_I2C_BUS 0 #define BOARD_TOUCHSCREEN_I2C_BUS 0
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
/* SD CARD gpio */ /* SD CARD gpio */
#define SDCARD_CD 81 #define SDCARD_CD 81

1
src/mainboard/intel/tglrvp/board_id.h
View File

@ -3,7 +3,6 @@
#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_
#define _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_
/* Board/FAB ID Command */ /* Board/FAB ID Command */
#define EC_FAB_ID_CMD 0x0D #define EC_FAB_ID_CMD 0x0D