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soc/intel/common/gpio: Support 4 bits GPIO pad mode configuration 

Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins
that native function 8 to 15 is assigned. This adds native function
definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support
4 bits pad mode configuration.

Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not
assigned, this change would not cause an issue but Kconfig option is
added to minimize an impact and support 4 bits pad mode configuration.

BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jamie Ryu 2022-08-02 09:14:23 -07:00 committed by Martin Roth
parent 34aa639a26
commit 4b8092aebb
2 changed files with 35 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/common/block/gpio/Kconfig
View File

@ -53,4 +53,12 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR
Starting with MTL SoC, the recommendation is to use PCR for locking down the Starting with MTL SoC, the recommendation is to use PCR for locking down the
GPIO configuration. GPIO configuration.
# Indicate if SoC supports 4 bits Pad Mode with PAD_CFG_DW0 registers
config SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS
bool
default n
help
SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser
is 4 bits to support Native Function 1 to 15.
endif endif

37
src/soc/intel/common/block/include/intelblocks/gpio_defs.h
View File

@ -5,6 +5,8 @@
#include <intelblocks/gpio.h> #include <intelblocks/gpio.h>
#define _BIT_WIDTH(x) ((1 << (x)) - 1)
#define PAD_CFG0_TX_STATE_BIT 0 #define PAD_CFG0_TX_STATE_BIT 0
#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
#define PAD_CFG0_RX_STATE_BIT 1 #define PAD_CFG0_RX_STATE_BIT 1
@ -12,16 +14,31 @@
#define PAD_CFG0_TX_DISABLE (1 << 8) #define PAD_CFG0_TX_DISABLE (1 << 8)
#define PAD_CFG0_RX_DISABLE (1 << 9) #define PAD_CFG0_RX_DISABLE (1 << 9)
#define PAD_CFG0_MODE_SHIFT 10 #define PAD_CFG0_MODE_SHIFT 10
#define PAD_CFG0_MODE_MASK (7 << 10) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS)
#define PAD_CFG0_MODE_GPIO (0 << 10) #define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(4)
#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) #else
#define PAD_CFG0_MODE_NF1 (1 << 10) #define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(3)
#define PAD_CFG0_MODE_NF2 (2 << 10) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */
#define PAD_CFG0_MODE_NF3 (3 << 10) #define PAD_CFG0_MODE_MASK (PAD_CFG0_MODE_BIT_WIDTH << PAD_CFG0_MODE_SHIFT)
#define PAD_CFG0_MODE_NF4 (4 << 10) #define PAD_CFG0_MODE_FUNC(x) ((x) << PAD_CFG0_MODE_SHIFT)
#define PAD_CFG0_MODE_NF5 (5 << 10) #define PAD_CFG0_MODE_GPIO PAD_CFG0_MODE_FUNC(0)
#define PAD_CFG0_MODE_NF6 (6 << 10) #define PAD_CFG0_MODE_NF1 PAD_CFG0_MODE_FUNC(1)
#define PAD_CFG0_MODE_NF7 (7 << 10) #define PAD_CFG0_MODE_NF2 PAD_CFG0_MODE_FUNC(2)
#define PAD_CFG0_MODE_NF3 PAD_CFG0_MODE_FUNC(3)
#define PAD_CFG0_MODE_NF4 PAD_CFG0_MODE_FUNC(4)
#define PAD_CFG0_MODE_NF5 PAD_CFG0_MODE_FUNC(5)
#define PAD_CFG0_MODE_NF6 PAD_CFG0_MODE_FUNC(6)
#define PAD_CFG0_MODE_NF7 PAD_CFG0_MODE_FUNC(7)
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS)
#define PAD_CFG0_MODE_NF8 PAD_CFG0_MODE_FUNC(8)
#define PAD_CFG0_MODE_NF9 PAD_CFG0_MODE_FUNC(9)
#define PAD_CFG0_MODE_NF10 PAD_CFG0_MODE_FUNC(10)
#define PAD_CFG0_MODE_NF11 PAD_CFG0_MODE_FUNC(11)
#define PAD_CFG0_MODE_NF12 PAD_CFG0_MODE_FUNC(12)
#define PAD_CFG0_MODE_NF13 PAD_CFG0_MODE_FUNC(13)
#define PAD_CFG0_MODE_NF14 PAD_CFG0_MODE_FUNC(14)
#define PAD_CFG0_MODE_NF15 PAD_CFG0_MODE_FUNC(15)
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */
#define PAD_CFG0_ROUTE_MASK (0xF << 17) #define PAD_CFG0_ROUTE_MASK (0xF << 17)
#define PAD_CFG0_ROUTE_NMI (1 << 17) #define PAD_CFG0_ROUTE_NMI (1 << 17)
#define PAD_CFG0_ROUTE_SMI (1 << 18) #define PAD_CFG0_ROUTE_SMI (1 << 18)