added chipsetinit function, many defines. addec call to chipsetinit to
northbridge.c builds fine on lippert git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
45f6c5e3d4
commit
4b8cf1d30a
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@ -683,4 +683,417 @@
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#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
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/* I don't mind if somebody decides this needs to be in a seperate file. I don't see much point
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* in it, either.
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* RGM
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*/
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#define Cx5535_ID ( 0x002A100B)
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#define Cx5536_ID ( 0x208F1022)
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/* Cs5535 as follows. */
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/* SB_GLIU*/
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/* port0 - GLIU*/
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/* port1 - GLPCI*/
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/* port2 - USB Controller #2*/
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/* port3 - ATA-5 Controller*/
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/* port4 - MDD*/
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/* port5 - AC97*/
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/* port6 - USB Controller #1*/
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/* port7 - GLCP*/
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/* SouthBridge Equates*/
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/* MSR_SB and SB_SHIFT are located in CPU.inc*/
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#define MSR_SB_GLIU ( (9 << 14) + MSR_SB /* fake out just like GL0 on CPU.*/)
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#define MSR_SB_GLPCI ( MSR_SB /* don't go to the GLIU*/)
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#define MSR_SB_USB2 ( (2 << SB_SHIFT) + MSR_SB)
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#define MSR_SB_ATA ( (3 << SB_SHIFT) + MSR_SB)
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#define MSR_SB_MDD ( (4 << SB_SHIFT) + MSR_SB)
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#define MSR_SB_AC97 ( (5 << SB_SHIFT) + MSR_SB)
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#define MSR_SB_USB1 ( (6 << SB_SHIFT) + MSR_SB)
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#define MSR_SB_GLCP ( (7 << SB_SHIFT) + MSR_SB)
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/* */
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/* GLIU*/
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/* */
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#define GLIU_SB_GLD_MSR_CAP ( MSR_SB_GLIU + 0x00)
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#define GLIU_SB_GLD_MSR_CONF ( MSR_SB_GLIU + 0x01)
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#define GLIU_SB_GLD_MSR_PM ( MSR_SB_GLIU + 0x04)
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/* */
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/* USB1*/
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/* */
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#define USB1_SB_GLD_MSR_CAP ( MSR_SB_USB1 + 0x00)
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#define USB1_SB_GLD_MSR_CONF ( MSR_SB_USB1 + 0x01)
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#define USB1_SB_GLD_MSR_PM ( MSR_SB_USB1 + 0x04)
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/* */
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/* USB2*/
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/* */
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#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00)
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#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01)
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#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04)
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/* */
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/* ATA*/
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/* */
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#define ATA_SB_GLD_MSR_CAP ( MSR_SB_ATA + 0x00)
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#define ATA_SB_GLD_MSR_CONF ( MSR_SB_ATA + 0x01)
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#define ATA_SB_GLD_MSR_ERR ( MSR_SB_ATA + 0x03)
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#define ATA_SB_GLD_MSR_PM ( MSR_SB_ATA + 0x04)
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/* */
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/* AC97*/
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/* */
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#define AC97_SB_GLD_MSR_CAP ( MSR_SB_AC97 + 0x00)
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#define AC97_SB_GLD_MSR_CONF ( MSR_SB_AC97 + 0x01)
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#define AC97_SB_GLD_MSR_PM ( MSR_SB_AC97 + 0x04)
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/* */
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/* GLPCI*/
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/* */
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#define GLPCI_SB_GLD_MSR_CAP ( MSR_SB_GLPCI + 0x00)
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#define GLPCI_SB_GLD_MSR_CONF ( MSR_SB_GLPCI + 0x01)
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#define GLPCI_SB_GLD_MSR_PM ( MSR_SB_GLPCI + 0x04)
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#define GLPCI_SB_CTRL ( MSR_SB_GLPCI + 0x10)
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#define GLPCI_CRTL_PPIDE_SET ( 1 << 17)
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/* */
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/* GLCP*/
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/* */
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#define GLCP_SB_GLD_MSR_CAP ( MSR_SB_GLCP + 0x00)
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#define GLCP_SB_GLD_MSR_CONF ( MSR_SB_GLCP + 0x01)
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#define GLCP_SB_GLD_MSR_PM ( MSR_SB_GLCP + 0x04)
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/* */
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/* MDD*/
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/* */
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#define MDD_SB_GLD_MSR_CAP ( MSR_SB_MDD + 0x00)
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#define MDD_SB_GLD_MSR_CONF ( MSR_SB_MDD + 0x01)
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#define MDD_SB_GLD_MSR_PM ( MSR_SB_MDD + 0x04)
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#define LBAR_EN ( 0x01)
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#define IO_MASK ( 0x1f)
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#define MEM_MASK ( 0x0FFFFF)
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#define MDD_LBAR_IRQ ( MSR_SB_MDD + 0x08)
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#define MDD_LBAR_KEL1 ( MSR_SB_MDD + 0x09)
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#define MDD_LBAR_KEL2 ( MSR_SB_MDD + 0x0A)
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#define MDD_LBAR_SMB ( MSR_SB_MDD + 0x0B)
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#define MDD_LBAR_GPIO ( MSR_SB_MDD + 0x0C)
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#define MDD_LBAR_MFGPT ( MSR_SB_MDD + 0x0D)
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#define MDD_LBAR_ACPI ( MSR_SB_MDD + 0x0E)
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#define MDD_LBAR_PMS ( MSR_SB_MDD + 0x0F)
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#define MDD_LBAR_FLSH0 ( MSR_SB_MDD + 0x010)
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#define MDD_LBAR_FLSH1 ( MSR_SB_MDD + 0x011)
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#define MDD_LBAR_FLSH2 ( MSR_SB_MDD + 0x012)
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#define MDD_LBAR_FLSH3 ( MSR_SB_MDD + 0x013)
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#define MDD_LEG_IO ( MSR_SB_MDD + 0x014)
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#define MDD_PIN_OPT ( MSR_SB_MDD + 0x015)
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#define MDD_SOFT_IRQ ( MSR_SB_MDD + 0x016)
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#define MDD_SOFT_RESET ( MSR_SB_MDD + 0x017)
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#define MDD_NORF_CNTRL ( MSR_SB_MDD + 0x018)
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#define MDD_NORF_T01 ( MSR_SB_MDD + 0x019)
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#define MDD_NORF_T23 ( MSR_SB_MDD + 0x01A)
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#define MDD_NANDF_DATA ( MSR_SB_MDD + 0x01B)
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#define MDD_NADF_CNTL ( MSR_SB_MDD + 0x01C)
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#define MDD_AC_DMA ( MSR_SB_MDD + 0x01E)
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#define MDD_KEL_CNTRL ( MSR_SB_MDD + 0x01F)
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#define MDD_IRQM_YLOW ( MSR_SB_MDD + 0x020)
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#define MDD_IRQM_YHIGH ( MSR_SB_MDD + 0x021)
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#define MDD_IRQM_ZLOW ( MSR_SB_MDD + 0x022)
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#define MDD_IRQM_ZHIGH ( MSR_SB_MDD + 0x023)
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#define MDD_IRQM_PRIM ( MSR_SB_MDD + 0x024)
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#define MDD_IRQM_LPC ( MSR_SB_MDD + 0x025)
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#define MDD_IRQM_LXIRR ( MSR_SB_MDD + 0x026)
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#define MDD_IRQM_HXIRR ( MSR_SB_MDD + 0x027)
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#define MDD_MFGPT_IRQ ( MSR_SB_MDD + 0x028)
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#define MDD_MFGPT_NR ( MSR_SB_MDD + 0x029)
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#define MDD_MFGPT_RES0 ( MSR_SB_MDD + 0x02A)
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#define MDD_MFGPT_RES1 ( MSR_SB_MDD + 0x02B)
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#define MDD_FLOP_S3F2 ( MSR_SB_MDD + 0x030)
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#define MDD_FLOP_S3F7 ( MSR_SB_MDD + 0x031)
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#define MDD_FLOP_S372 ( MSR_SB_MDD + 0x032)
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#define MDD_FLOP_S377 ( MSR_SB_MDD + 0x033)
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#define MDD_PIC_S ( MSR_SB_MDD + 0x034)
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#define MDD_PIT_S ( MSR_SB_MDD + 0x036)
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#define MDD_PIT_CNTRL ( MSR_SB_MDD + 0x037)
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#define MDD_UART1_MOD ( MSR_SB_MDD + 0x038)
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#define MDD_UART1_DON ( MSR_SB_MDD + 0x039)
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#define MDD_UART1_CONF ( MSR_SB_MDD + 0x03A)
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#define MDD_UART2_MOD ( MSR_SB_MDD + 0x03C)
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#define MDD_UART2_DON ( MSR_SB_MDD + 0x03D)
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#define MDD_UART2_CONF ( MSR_SB_MDD + 0x03E)
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#define MDD_DMA_MAP ( MSR_SB_MDD + 0x040)
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#define MDD_DMA_SHAD1 ( MSR_SB_MDD + 0x041)
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#define MDD_DMA_SHAD2 ( MSR_SB_MDD + 0x042)
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#define MDD_DMA_SHAD3 ( MSR_SB_MDD + 0x043)
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#define MDD_DMA_SHAD4 ( MSR_SB_MDD + 0x044)
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#define MDD_DMA_SHAD5 ( MSR_SB_MDD + 0x045)
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#define MDD_DMA_SHAD6 ( MSR_SB_MDD + 0x046)
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#define MDD_DMA_SHAD7 ( MSR_SB_MDD + 0x047)
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#define MDD_DMA_SHAD8 ( MSR_SB_MDD + 0x048)
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#define MDD_DMA_SHAD9 ( MSR_SB_MDD + 0x049)
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#define MDD_LPC_EADDR ( MSR_SB_MDD + 0x04C)
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#define MDD_LPC_ESTAT ( MSR_SB_MDD + 0x04D)
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#define MDD_LPC_SIRQ ( MSR_SB_MDD + 0x04E)
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#define MDD_LPC_RES ( MSR_SB_MDD + 0x04F)
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#define MDD_PML_TMR ( MSR_SB_MDD + 0x050)
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#define MDD_RTC_RAM_LO_CK ( MSR_SB_MDD + 0x054)
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#define MDD_RTC_DOMA_IND ( MSR_SB_MDD + 0x055)
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#define MDD_RTC_MONA_IND ( MSR_SB_MDD + 0x056)
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#define MDD_RTC_CENTURY_OFFSET ( MSR_SB_MDD + 0x057)
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/* */
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/* LBAR IO + MEMORY MAP*/
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/* */
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#define SMBUS_BASE ( 0x6000)
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#define GPIO_BASE ( 0x6100)
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#define MFGPT_BASE ( 0x6200)
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#define IRQMAP_BASE ( 0x6300)
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#define PMLogic_BASE ( 0x9D00)
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/* ***********************************************************/
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/* LBUS Device Equates - */
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/* ***********************************************************/
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/* */
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/* SMBus*/
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/* */
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#define SMBUS_SMBSDA ( SMBUS_BASE + 0x00)
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#define SMBUS_SMBST ( SMBUS_BASE + 0x01)
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#define SMBST_SLVSTP_SET ( 1 << 7)
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#define SMBST_SDAST_SET ( 1 << 6)
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#define SMBST_BER_SET ( 1 << 5)
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#define SMBST_NEGACK_SET ( 1 << 4)
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#define SMBST_STASTR_SET ( 1 << 3)
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#define SMBST_NMATCH_SET ( 1 << 2)
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#define SMBST_MASTER_SET ( 1 << 1)
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#define SMBST_XMIT_SET ( 1 << 0)
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#define SMBUS_SMBCST ( SMBUS_BASE + 0x02)
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#define SMBCST_TGSCL_SET ( 1 << 5)
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#define SMBCST_TSDA_SET ( 1 << 4)
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#define SMBCST_GCMTCH_SET ( 1 << 3)
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#define SMBCST_MATCH_SET ( 1 << 2)
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#define SMBCST_BB_SET ( 1 << 1)
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#define SMBCST_BUSY_SET ( 1 << 0)
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#define SMBUS_SMBCTL1 ( SMBUS_BASE + 0x03)
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#define SMBCTL1_STASTRE_SET ( 1 << 7)
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#define SMBCTL1_NMINTE_SET ( 1 << 6)
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#define SMBCTL1_GCMEN_SET ( 1 << 5)
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#define SMBCTL1_RECACK_SET ( 1 << 4)
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#define SMBCTL1_DMAEN_SET ( 1 << 3)
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#define SMBCTL1_INTEN_SET ( 1 << 2)
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#define SMBCTL1_STOP_SET ( 1 << 1)
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#define SMBCTL1_START_SET ( 1 << 0)
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#define SMBUS_SMBADDR ( SMBUS_BASE + 0x04)
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#define SMBADDR_SAEN_SET ( 1 << 7)
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#define SMBUS_SMBCTL2 ( SMBUS_BASE + 0x05)
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#define SMBCTL2_SCLFRQ_SHIFT ( 1 << 1)
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#define SMBCTL2_ENABLE_SET ( 1 << 0)
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/* */
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/* GPIO*/
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/* */
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#define GPIOL_0_SET ( 1 << 0)
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#define GPIOL_1_SET ( 1 << 1)
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#define GPIOL_2_SET ( 1 << 2)
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#define GPIOL_3_SET ( 1 << 3)
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#define GPIOL_4_SET ( 1 << 4)
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#define GPIOL_5_SET ( 1 << 5)
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#define GPIOL_6_SET ( 1 << 6)
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#define GPIOL_7_SET ( 1 << 7)
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#define GPIOL_8_SET ( 1 << 8)
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#define GPIOL_9_SET ( 1 << 9)
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#define GPIOL_10_SET ( 1 << 10)
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#define GPIOL_11_SET ( 1 << 11)
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#define GPIOL_12_SET ( 1 << 12)
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#define GPIOL_13_SET ( 1 << 13)
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#define GPIOL_14_SET ( 1 << 14)
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#define GPIOL_15_SET ( 1 << 15)
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#define GPIOL_0_CLEAR ( 1 << 16)
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#define GPIOL_1_CLEAR ( 1 << 17)
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#define GPIOL_2_CLEAR ( 1 << 18)
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#define GPIOL_3_CLEAR ( 1 << 19)
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#define GPIOL_4_CLEAR ( 1 << 20)
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#define GPIOL_5_CLEAR ( 1 << 21)
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#define GPIOL_6_CLEAR ( 1 << 22)
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#define GPIOL_7_CLEAR ( 1 << 23)
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#define GPIOL_8_CLEAR ( 1 << 24)
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#define GPIOL_9_CLEAR ( 1 << 25)
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#define GPIOL_10_CLEAR ( 1 << 26)
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#define GPIOL_11_CLEAR ( 1 << 27)
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#define GPIOL_12_CLEAR ( 1 << 28)
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#define GPIOL_13_CLEAR ( 1 << 29)
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#define GPIOL_14_CLEAR ( 1 << 30)
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#define GPIOL_15_CLEAR ( 1 << 31)
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#define GPIOH_16_SET ( 1 << 0)
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#define GPIOH_17_SET ( 1 << 1)
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#define GPIOH_18_SET ( 1 << 2)
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#define GPIOH_19_SET ( 1 << 3)
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#define GPIOH_20_SET ( 1 << 4)
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#define GPIOH_21_SET ( 1 << 5)
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#define GPIOH_22_SET ( 1 << 6)
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#define GPIOH_23_SET ( 1 << 7)
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#define GPIOH_24_SET ( 1 << 8)
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#define GPIOH_25_SET ( 1 << 9)
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#define GPIOH_26_SET ( 1 << 10)
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#define GPIOH_27_SET ( 1 << 11)
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#define GPIOH_28_SET ( 1 << 12)
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#define GPIOH_29_SET ( 1 << 13)
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#define GPIOH_30_SET ( 1 << 14)
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#define GPIOH_31_SET ( 1 << 15)
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#define GPIOH_16_CLEAR ( 1 << 16)
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#define GPIOH_17_CLEAR ( 1 << 17)
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#define GPIOH_18_CLEAR ( 1 << 18)
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#define GPIOH_19_CLEAR ( 1 << 19)
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#define GPIOH_20_CLEAR ( 1 << 20)
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#define GPIOH_21_CLEAR ( 1 << 21)
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#define GPIOH_22_CLEAR ( 1 << 22)
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#define GPIOH_23_CLEAR ( 1 << 23)
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#define GPIOH_24_CLEAR ( 1 << 24)
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#define GPIOH_25_CLEAR ( 1 << 25)
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#define GPIOH_26_CLEAR ( 1 << 26)
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#define GPIOH_27_CLEAR ( 1 << 27)
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#define GPIOH_28_CLEAR ( 1 << 28)
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#define GPIOH_29_CLEAR ( 1 << 29)
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#define GPIOH_30_CLEAR ( 1 << 30)
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#define GPIOH_31_CLEAR ( 1 << 31)
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/* GPIO LOW Bank Bit Registers*/
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#define GPIOL_OUTPUT_VALUE ( GPIO_BASE + 0x00)
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#define GPIOL_OUTPUT_ENABLE ( GPIO_BASE + 0x04)
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#define GPIOL_OUT_OPENDRAIN ( GPIO_BASE + 0x08)
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#define GPIOL_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x0C)
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#define GPIOL_OUT_AUX1_SELECT ( GPIO_BASE + 0x10)
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#define GPIOL_OUT_AUX2_SELECT ( GPIO_BASE + 0x14)
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#define GPIOL_PULLUP_ENABLE ( GPIO_BASE + 0x18)
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#define GPIOL_PULLDOWN_ENABLE ( GPIO_BASE + 0x1C)
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#define GPIOL_INPUT_ENABLE ( GPIO_BASE + 0x20)
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#define GPIOL_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x24)
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#define GPIOL_IN_FILTER_ENABLE ( GPIO_BASE + 0x28)
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#define GPIOL_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x2C)
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#define GPIOL_READ_BACK ( GPIO_BASE + 0x30)
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#define GPIOL_IN_AUX1_SELECT ( GPIO_BASE + 0x34)
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#define GPIOL_EVENTS_ENABLE ( GPIO_BASE + 0x38)
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#define GPIOL_LOCK_ENABLE ( GPIO_BASE + 0x3C)
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#define GPIOL_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x40)
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#define GPIOL_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x44)
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#define GPIOL_IN_POSEDGE_STATUS ( GPIO_BASE + 0x48)
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#define GPIOL_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x4C)
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/* GPIO High Bank Bit Registers*/
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#define GPIOH_OUTPUT_VALUE ( GPIO_BASE + 0x80)
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#define GPIOH_OUTPUT_ENABLE ( GPIO_BASE + 0x84)
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#define GPIOH_OUT_OPENDRAIN ( GPIO_BASE + 0x88)
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#define GPIOH_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x8C)
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#define GPIOH_OUT_AUX1_SELECT ( GPIO_BASE + 0x90)
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#define GPIOH_OUT_AUX2_SELECT ( GPIO_BASE + 0x94)
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#define GPIOH_PULLUP_ENABLE ( GPIO_BASE + 0x98)
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#define GPIOH_PULLDOWN_ENABLE ( GPIO_BASE + 0x9C)
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#define GPIOH_INPUT_ENABLE ( GPIO_BASE + 0x0A0)
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#define GPIOH_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x0A4)
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#define GPIOH_IN_FILTER_ENABLE ( GPIO_BASE + 0x0A8)
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#define GPIOH_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x0AC)
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#define GPIOH_READ_BACK ( GPIO_BASE + 0x0B0)
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#define GPIOH_IN_AUX1_SELECT ( GPIO_BASE + 0x0B4)
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#define GPIOH_EVENTS_ENABLE ( GPIO_BASE + 0x0B8)
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#define GPIOH_LOCK_ENABLE ( GPIO_BASE + 0x0BC)
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#define GPIOH_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x0C0)
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#define GPIOH_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x0C4)
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#define GPIOH_IN_POSEDGE_STATUS ( GPIO_BASE + 0x0C8)
|
||||
#define GPIOH_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x0CC)
|
||||
|
||||
/* Input Conditioning Function Registers*/
|
||||
#define GPIO_00_FILTER_AMOUNT ( GPIO_BASE + 0x50)
|
||||
#define GPIO_00_FILTER_COUNT ( GPIO_BASE + 0x52)
|
||||
#define GPIO_00_EVENT_COUNT ( GPIO_BASE + 0x54)
|
||||
#define GPIO_00_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x56)
|
||||
#define GPIO_01_FILTER_AMOUNT ( GPIO_BASE + 0x58)
|
||||
#define GPIO_01_FILTER_COUNT ( GPIO_BASE + 0x5A)
|
||||
#define GPIO_01_EVENT_COUNT ( GPIO_BASE + 0x5C)
|
||||
#define GPIO_01_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x5E)
|
||||
#define GPIO_02_FILTER_AMOUNT ( GPIO_BASE + 0x60)
|
||||
#define GPIO_02_FILTER_COUNT ( GPIO_BASE + 0x62)
|
||||
#define GPIO_02_EVENT_COUNT ( GPIO_BASE + 0x64)
|
||||
#define GPIO_02_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x66)
|
||||
#define GPIO_03_FILTER_AMOUNT ( GPIO_BASE + 0x68)
|
||||
#define GPIO_03_FILTER_COUNT ( GPIO_BASE + 0x6A)
|
||||
#define GPIO_03_EVENT_COUNT ( GPIO_BASE + 0x6C)
|
||||
#define GPIO_03_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x6E)
|
||||
#define GPIO_04_FILTER_AMOUNT ( GPIO_BASE + 0x70)
|
||||
#define GPIO_04_FILTER_COUNT ( GPIO_BASE + 0x72)
|
||||
#define GPIO_04_EVENT_COUNT ( GPIO_BASE + 0x74)
|
||||
#define GPIO_04_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x76)
|
||||
#define GPIO_05_FILTER_AMOUNT ( GPIO_BASE + 0x78)
|
||||
#define GPIO_05_FILTER_COUNT ( GPIO_BASE + 0x7A)
|
||||
#define GPIO_05_EVENT_COUNT ( GPIO_BASE + 0x7C)
|
||||
#define GPIO_05_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x7E)
|
||||
#define GPIO_06_FILTER_AMOUNT ( GPIO_BASE + 0x0D0)
|
||||
#define GPIO_06_FILTER_COUNT ( GPIO_BASE + 0x0D2)
|
||||
#define GPIO_06_EVENT_COUNT ( GPIO_BASE + 0x0D4)
|
||||
#define GPIO_06_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0D6)
|
||||
#define GPIO_07_FILTER_AMOUNT ( GPIO_BASE + 0x0D8)
|
||||
#define GPIO_07_FILTER_COUNT ( GPIO_BASE + 0x0DA)
|
||||
#define GPIO_07_EVENT_COUNT ( GPIO_BASE + 0x0DC)
|
||||
#define GPIO_07_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0DE)
|
||||
|
||||
/* R/W GPIO Interrupt &PME Mapper Registers*/
|
||||
#define GPIO_MAPPER_X ( GPIO_BASE + 0x0E0)
|
||||
#define GPIO_MAPPER_Y ( GPIO_BASE + 0x0E4)
|
||||
#define GPIO_MAPPER_Z ( GPIO_BASE + 0x0E8)
|
||||
#define GPIO_MAPPER_W ( GPIO_BASE + 0x0EC)
|
||||
#define GPIO_FE_SELECT_0 ( GPIO_BASE + 0x0F0)
|
||||
#define GPIO_FE_SELECT_1 ( GPIO_BASE + 0x0F1)
|
||||
#define GPIO_FE_SELECT_2 ( GPIO_BASE + 0x0F2)
|
||||
#define GPIO_FE_SELECT_3 ( GPIO_BASE + 0x0F3)
|
||||
#define GPIO_FE_SELECT_4 ( GPIO_BASE + 0x0F4)
|
||||
#define GPIO_FE_SELECT_5 ( GPIO_BASE + 0x0F5)
|
||||
#define GPIO_FE_SELECT_6 ( GPIO_BASE + 0x0F6)
|
||||
#define GPIO_FE_SELECT_7 ( GPIO_BASE + 0x0F7)
|
||||
|
||||
/* Event Counter Decrement Registers*/
|
||||
#define GPIOL_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0F8)
|
||||
#define GPIOH_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0FC)
|
||||
|
||||
/* This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/
|
||||
#define FUNC0 ( 0x90)
|
||||
|
||||
|
||||
/* sworley, PMC register*/
|
||||
#define PM_SSD ( PMLogic_BASE + 0x00)
|
||||
#define PM_SCXA ( PMLogic_BASE + 0x04)
|
||||
#define PM_SCYA ( PMLogic_BASE + 0x08)
|
||||
#define PM_SODA ( PMLogic_BASE + 0x0C)
|
||||
#define PM_SCLK ( PMLogic_BASE + 0x10)
|
||||
#define PM_SED ( PMLogic_BASE + 0x14)
|
||||
#define PM_SCXD ( PMLogic_BASE + 0x18)
|
||||
#define PM_SCYD ( PMLogic_BASE + 0x1C)
|
||||
#define PM_SIDD ( PMLogic_BASE + 0x20)
|
||||
#define PM_WKD ( PMLogic_BASE + 0x30)
|
||||
#define PM_WKXD ( PMLogic_BASE + 0x34)
|
||||
#define PM_RD ( PMLogic_BASE + 0x38)
|
||||
#define PM_WKXA ( PMLogic_BASE + 0x3C)
|
||||
#define PM_FSD ( PMLogic_BASE + 0x40)
|
||||
#define PM_TSD ( PMLogic_BASE + 0x44)
|
||||
#define PM_PSD ( PMLogic_BASE + 0x48)
|
||||
#define PM_NWKD ( PMLogic_BASE + 0x4C)
|
||||
#define PM_AWKD ( PMLogic_BASE + 0x50)
|
||||
#define PM_SSC ( PMLogic_BASE + 0x54)
|
||||
|
||||
#endif /* CPU_AMD_GX2DEF_H */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
config chip.h
|
||||
object northbridge.o
|
||||
object northbridgeinit.o
|
||||
|
||||
object chipsetinit.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,298 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <bitops.h>
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
#include <cpu/amd/gx2def.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
|
||||
|
||||
/* the structs in this file only set msr.lo. But ... that may not always be true */
|
||||
|
||||
struct msrinit {
|
||||
unsigned long msrnum;
|
||||
msr_t msr;
|
||||
};
|
||||
|
||||
/* Master Configuration Register for Bus Masters.*/
|
||||
struct msrinit SB_MASTER_CONF_TABLE[] = {
|
||||
{USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, /* NOTE: Must be 1st entry in table*/
|
||||
{USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}},
|
||||
{ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000}},
|
||||
{AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}},
|
||||
{MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000}},
|
||||
/* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
|
||||
/* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
|
||||
/* GLIU_SB_GLD_MSR_CONF, 0x0*/
|
||||
{0,{0,0}}
|
||||
};
|
||||
|
||||
/* 5535_A3 Clock Gating*/
|
||||
struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
|
||||
{ USB1_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{ USB2_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{ GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}},
|
||||
{ GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{ GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}},
|
||||
{ MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}},
|
||||
{ ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{ AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{0,{0,0}}
|
||||
};
|
||||
|
||||
/* 5536 Clock Gating*/
|
||||
struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
|
||||
/* MSR Setting*/
|
||||
{ GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}},
|
||||
{ GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{ GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}},
|
||||
{ MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/
|
||||
{ ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{ AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
|
||||
{0,{0,0}}
|
||||
};
|
||||
|
||||
struct acpiinit {
|
||||
unsigned short ioreg;
|
||||
unsigned long regdata;
|
||||
unsigned short iolen;
|
||||
};
|
||||
|
||||
struct acpiinit acpi_init_table[] = {
|
||||
{ACPI_BASE+0x00, 0x01000000, 4},
|
||||
{ACPI_BASE+0x08, 0, 4},
|
||||
{ACPI_BASE+0x0C, 0, 4},
|
||||
{ACPI_BASE+0x1C, 0, 4},
|
||||
{ACPI_BASE+0x18, 0x0FFFFFFFF, 4},
|
||||
{ACPI_BASE+0x00, 0x0000FFFF, 4},
|
||||
|
||||
{PM_SCLK, 0x000000E00, 4},
|
||||
{PM_SED, 0x000004601, 4},
|
||||
{PM_SIDD, 0x000008C02, 4},
|
||||
{PM_WKD, 0x0000000A0, 4},
|
||||
{PM_WKXD, 0x0000000A0, 4},
|
||||
{0,0,0}
|
||||
};
|
||||
|
||||
/* return 1 if we are a 5536-based system */
|
||||
static int is_5536(void){
|
||||
msr_t msr;
|
||||
msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
|
||||
msr.lo >>= 20;
|
||||
printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
|
||||
return ((msr.lo&0xf) == 5);
|
||||
}
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * pmChipsetInit*/
|
||||
/* **/
|
||||
/* * Program ACPI LBAR and initialize ACPI registers.*/
|
||||
/* * */
|
||||
/* **/
|
||||
/* * Entry:*/
|
||||
/* * None*/
|
||||
/* **/
|
||||
/* * Exit:*/
|
||||
/* * None*/
|
||||
/* **/
|
||||
/* * Destroys:*/
|
||||
/* * None*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
pmChipsetInit(void) {
|
||||
unsigned long val = 0;
|
||||
unsigned short port;
|
||||
|
||||
port = (PMLogic_BASE + 0x010);
|
||||
val = 0x0E00 ; /* 1ms*/
|
||||
outl(val, port);
|
||||
|
||||
/* PM_WKXD*/
|
||||
/* Make sure bits[3:0]=0000b to clear the*/
|
||||
/* saved Sx state*/
|
||||
port = (PMLogic_BASE + 0x034);
|
||||
val = 0x0A0 ; /* 5ms*/
|
||||
outl(val, port);
|
||||
|
||||
/* PM_WKD*/
|
||||
port = (PMLogic_BASE + 0x030);
|
||||
outl(val, port);
|
||||
|
||||
/* PM_SED*/
|
||||
port = (PMLogic_BASE + 0x014);
|
||||
/* mov eax, 0x057642 ; 100ms, works*/
|
||||
val = 0x04601 ; /* 5ms*/
|
||||
outl(val, port);
|
||||
|
||||
/* PM_SIDD*/
|
||||
port = (PMLogic_BASE + 0x020);
|
||||
/* mov eax, 0x0AEC84 ; 200ms, works*/
|
||||
val = 0x08C02 ; /* 10ms*/
|
||||
outl(val, port);
|
||||
|
||||
/* GPIO24 OUT_AUX1 function is the external signal for 5535's vsb_working_aux*/
|
||||
/* which is de-asserted when 5535 enters Standby(S3 or S5) state.*/
|
||||
/* On Hawk, GPIO24 controls all voltage rails except Vmem and Vstandby. This means*/
|
||||
/* GX2 will be fully de-powered if this control de-asserts in S3/S5.*/
|
||||
/* */
|
||||
/* GPIO24 is setup in preChipsetInit for two reasons*/
|
||||
/* 1. GPIO24 at reset defaults to disabled, since this signal is vsb_work_aux on*/
|
||||
/* Hawk it controls the FET's for all voltage rails except Vstanby & Vmem.*/
|
||||
/* BIOS needs to enable GPIO24 as OUT_AUX1 & OUTPUT_EN early so it is driven*/
|
||||
/* by 5535.*/
|
||||
/* 2. Non-PM builds will require GPIO24 enabled for instant-off power button*/
|
||||
/* */
|
||||
|
||||
/* GPIO11 OUT_AUX1 function is the external signal for 5535's slp_clk_n which is asserted*/
|
||||
/* when 5535 enters Sleep(S1) state.*/
|
||||
/* On Hawk, GPIO11 is connected to control input of external clock generator*/
|
||||
/* for 14MHz, PCI, USB & LPC clocks.*/
|
||||
/* Programming of GPIO11 will be done by VSA PM code. During VSA Init. BIOS writes*/
|
||||
/* PM Core Virual Register indicating if S1 Clocks should be On or Off. This is based*/
|
||||
/* on a Setup item. We do not want to leave GPIO11 enabled because of a Hawk board*/
|
||||
/* problem. With GPIO11 enabled in S3, something is back-driving GPIO11 causing it to*/
|
||||
/* float to 1.6-1.7V.*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * ChipsetGeodeLinkInit*/
|
||||
/* * Handle chipset specific GeodeLink settings here. */
|
||||
/* * Called from GeodeLink init code.*/
|
||||
/* **/
|
||||
/* * Entry:*/
|
||||
/* * Exit:*/
|
||||
/* * Destroys: GS*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
ChipsetGeodeLinkInit(void){
|
||||
msr_t msr;
|
||||
unsigned long msrnum;
|
||||
unsigned long totalmem;
|
||||
|
||||
if (is_5536())
|
||||
return;
|
||||
/* SWASIF for A1 DMA */
|
||||
/* Set all memory to "just above systop" PCI so DMA will work*/
|
||||
/* check A1*/
|
||||
msrnum = MSR_SB_GLCP + 0x17;
|
||||
msr = rdmsr(msrnum);
|
||||
if ((msr.lo&0xff) == 0x11)
|
||||
return;
|
||||
|
||||
totalmem = sizeram() << 20 - 1;
|
||||
totalmem >>= 12;
|
||||
totalmem = ~totalmem;
|
||||
totalmem &= 0xfffff;
|
||||
msr.lo = totalmem;
|
||||
msr.hi = 0x20000000; /* Port 1 (PCI)*/
|
||||
msrnum = MSR_SB_GLIU + 0x20; /* */;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
||||
void
|
||||
chipsetinit (void){
|
||||
msr_t msr;
|
||||
struct msrinit *csi;
|
||||
int i;
|
||||
unsigned long msrnum;
|
||||
|
||||
outb( P80_CHIPSET_INIT, 0x80);
|
||||
ChipsetGeodeLinkInit();
|
||||
|
||||
/* we hope NEVER to be in linuxbios when S3 resumes
|
||||
if (! IsS3Resume()) */
|
||||
{
|
||||
struct acpiinit *aci = acpi_init_table;
|
||||
while (aci->ioreg){
|
||||
if (aci->iolen == 2) {
|
||||
outw(aci->regdata, aci->ioreg);
|
||||
inw(aci->ioreg);
|
||||
} else {
|
||||
outl(aci->regdata, aci->ioreg);
|
||||
inl(aci->ioreg);
|
||||
}
|
||||
}
|
||||
|
||||
pmChipsetInit();
|
||||
}
|
||||
|
||||
/* for later ... if 5536 set_usb_20(); */
|
||||
|
||||
/* Setup USB. Need more details. #118.18*/
|
||||
msrnum = MSR_SB_USB1 + 8;
|
||||
msr.lo = 0x00012090;
|
||||
msr.hi = 0;
|
||||
wrmsr(msrnum, msr);
|
||||
msrnum = MSR_SB_USB2 + 8;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* set hd IRQ */
|
||||
outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE);
|
||||
outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
|
||||
|
||||
/* Allow IO read and writes during a ATA DMA operation.*/
|
||||
/* This could be done in the HD rom but do it here for easier debugging.*/
|
||||
|
||||
msrnum = ATA_SB_GLD_MSR_ERR;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~0x100;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Enable Post Primary IDE.*/
|
||||
msrnum = GLPCI_SB_CTRL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= GLPCI_CRTL_PPIDE_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
/* Set up Master Configuration Register*/
|
||||
/* If 5536, use same master config settings as 5535, except for OHCI MSRs*/
|
||||
if (is_5536())
|
||||
i = 2;
|
||||
else
|
||||
i = 0;
|
||||
|
||||
csi = &SB_MASTER_CONF_TABLE[i];
|
||||
for(; csi->msrnum; csi++){
|
||||
msr.lo = csi->msr.lo;
|
||||
msr.hi = csi->msr.hi;
|
||||
wrmsr(csi->msrnum, msr);
|
||||
}
|
||||
|
||||
|
||||
/* Flash Setup*/
|
||||
printk_err("NOT DOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n");
|
||||
// ChipsetFlashSetup();
|
||||
|
||||
|
||||
|
||||
/* */
|
||||
/* Set up Hardware Clock Gating*/
|
||||
/* */
|
||||
/* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
|
||||
{
|
||||
if (is_5536())
|
||||
csi = CS5536_CLOCK_GATING_TABLE;
|
||||
else
|
||||
csi = CS5535_CLOCK_GATING_TABLE;
|
||||
|
||||
for(; csi->msrnum; csi++){
|
||||
msr.lo = csi->msr.lo;
|
||||
msr.hi = csi->msr.hi;
|
||||
wrmsr(csi->msrnum, msr);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -414,6 +414,8 @@ static struct device_operations cpu_bus_ops = {
|
|||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
void chipsetInit (void);
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
printk_debug("gx2 north: enable_dev\n");
|
||||
|
|
@ -423,6 +425,7 @@ static void enable_dev(struct device *dev)
|
|||
printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
|
||||
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
|
||||
cpubug();
|
||||
chipsetinit();
|
||||
setup_gx2();
|
||||
/* do this here for now -- this chip really breaks our device model */
|
||||
setup_realmode_idt();
|
||||
|
|
|
|||
Loading…
Reference in New Issue