diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index da0b4e10c6..6112e6a27d 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -129,6 +129,21 @@ static const struct vr_lookup vr_config_ll[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
 	{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 };
 
 static const struct vr_lookup vr_config_icc[] = {
@@ -150,6 +165,21 @@ static const struct vr_lookup vr_config_icc[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
 	{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 55) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_ICC(240, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_ICC(154, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_ICC(240, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_ICC(220, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_ICC(145, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_ICC(175, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_ICC(151, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_ICC(100, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_ICC(110, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_ICC(110, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_ICC(90, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_ICC(49, 30) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_ICC(37, 30) },
 };
 
 static const struct vr_lookup vr_config_tdc_timewindow[] = {
@@ -171,6 +201,21 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 	{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 };
 
 static const struct vr_lookup vr_config_tdc_currentlimit[] = {
@@ -192,6 +237,21 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
 	{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
 	{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) },
 	{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
+	{ PCI_DID_INTEL_ADL_S_ID_1,  35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 109) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 77) },
+	{ PCI_DID_INTEL_ADL_S_ID_3,  35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 49) },
+	{ PCI_DID_INTEL_ADL_S_ID_8,  125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 96) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 65,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 66) },
+	{ PCI_DID_INTEL_ADL_S_ID_10, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 44) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 60,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 58,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 59) },
+	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 39) },
+	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) },
 };
 
 void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,