From 4b9fa2d6ea6107cf0c94b116dfffa553075fcded Mon Sep 17 00:00:00 2001
From: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Date: Fri, 13 Mar 2020 00:54:30 -0700
Subject: [PATCH] soc/intel/tigerlake: Update Cpu Ratio settings

Add config to override CpuRatio or setting CpuRatio to
allowed maximum processor non-turbo ratio.

BUG=151175469
BRANCH=none
TEST=Build and boot tglrvp and observe there is no extra reset
in meminit.

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/chip.h                    | 12 ++++++++++++
 src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 9fc70f8a46..5e010bda59 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -285,6 +285,18 @@ struct soc_intel_tigerlake_config {
 	 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
 	 * accordingly */
 	uint8_t HybridStorageMode;
+
+	/*
+	 * Override CPU flex ratio value:
+	 * CPU ratio value controls the maximum processor non-turbo ratio.
+	 * Valid Range 0 to 63.
+	 * In general descriptor provides option to set default cpu flex ratio.
+	 * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
+	 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+	 * Only override CPU flex ratio to not boot with non-turbo max.
+	 */
+	uint8_t cpu_ratio_override;
+
 };
 
 typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 3872b61cf7..c5629a51c6 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -15,9 +15,11 @@
 
 #include <assert.h>
 #include <console/console.h>
+#include <cpu/x86/msr.h>
 #include <fsp/util.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/iomap.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
@@ -38,6 +40,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
 	m_cfg->RMT = config->RMT;
 
+	/* CpuRatio Settings */
+	if (config->cpu_ratio_override) {
+		m_cfg->CpuRatio = config->cpu_ratio_override;
+	} else {
+		/* Set CpuRatio to match existing MSR value */
+		msr_t flex_ratio;
+		flex_ratio = rdmsr(MSR_FLEX_RATIO);
+		m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+	}
+
 	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
 		if (config->PcieRpEnable[i])
 			mask |= (1 << i);