intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This commit is contained in:
Stefan Reinauer
parent
083da160af
commit
4bab6e79b0
|
|
@ -25,8 +25,8 @@
|
|||
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
|
||||
#elif CONFIG_SOUTHBRIDGE_INTEL_I82801DX
|
||||
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
|
||||
#elif CONFIG_SOUTHBRIDGE_INTEL_SCH
|
||||
#include "../../../southbridge/intel/sch/sch.h"
|
||||
#elif CONFIG_SOC_INTEL_SCH
|
||||
#include "../../../soc/intel/sch/sch.h"
|
||||
#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
|
||||
#include "../../../southbridge/intel/i82801ix/i82801ix.h"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -4,8 +4,7 @@ if BOARD_IWAVE_RAINBOW_G6
|
|||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_441
|
||||
select NORTHBRIDGE_INTEL_SCH
|
||||
select SOUTHBRIDGE_INTEL_SCH
|
||||
select SOC_INTEL_SCH
|
||||
select HAVE_PIRQ_TABLE
|
||||
# select HAVE_MP_TABLE
|
||||
select UDELAY_LAPIC
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include <device/pci_ids.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
#include "southbridge/intel/sch/nvs.h"
|
||||
#include "soc/intel/sch/nvs.h"
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t * gnvs)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,8 +1,18 @@
|
|||
chip northbridge/intel/sch
|
||||
chip soc/intel/sch
|
||||
# IGD Displays
|
||||
register "gfx.ndid" = "3"
|
||||
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
|
||||
|
||||
# PIRQ routing
|
||||
register "pirqa_routing" = "0xa"
|
||||
register "pirqb_routing" = "0xb"
|
||||
register "pirqc_routing" = "0x5"
|
||||
register "pirqd_routing" = "0xf"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_441
|
||||
device lapic 0 on end
|
||||
|
|
@ -13,29 +23,18 @@ chip northbridge/intel/sch
|
|||
device pci 00.0 on end # host bridge
|
||||
device pci 02.0 on end # Integrated Graphics and Video Device
|
||||
|
||||
chip southbridge/intel/sch
|
||||
register "pirqa_routing" = "0xa"
|
||||
register "pirqb_routing" = "0xb"
|
||||
register "pirqc_routing" = "0x5"
|
||||
register "pirqd_routing" = "0xf"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
device pci 1a.0 on end # 26 0 USB Client
|
||||
device pci 1b.0 on end # 27 0 HD Audio Controller
|
||||
device pci 1c.0 on end # 28 0 PCI Express Port 1
|
||||
device pci 1c.1 on end # 28 1 PCI Express Port 2
|
||||
device pci 1d.0 on end # USB Classic UHCI Controller 1
|
||||
device pci 1d.1 on end # USB Classic UHCI Controller 2
|
||||
device pci 1d.2 on end # USB Classic UHCI Controller 3
|
||||
device pci 1d.7 on end # USB2 EHCI Controller
|
||||
device pci 1e.0 on end # SDIO/MMC Port 0
|
||||
device pci 1e.1 on end # SDIO/MMC Port 1
|
||||
device pci 1e.2 on end # SDIO/MMC Port 2
|
||||
device pci 1f.0 on end # LPC bridge
|
||||
device pci 1f.1 on end # PATA Controller
|
||||
end
|
||||
device pci 1a.0 on end # 26 0 USB Client
|
||||
device pci 1b.0 on end # 27 0 HD Audio Controller
|
||||
device pci 1c.0 on end # 28 0 PCI Express Port 1
|
||||
device pci 1c.1 on end # 28 1 PCI Express Port 2
|
||||
device pci 1d.0 on end # USB Classic UHCI Controller 1
|
||||
device pci 1d.1 on end # USB Classic UHCI Controller 2
|
||||
device pci 1d.2 on end # USB Classic UHCI Controller 3
|
||||
device pci 1d.7 on end # USB2 EHCI Controller
|
||||
device pci 1e.0 on end # SDIO/MMC Port 0
|
||||
device pci 1e.1 on end # SDIO/MMC Port 1
|
||||
device pci 1e.2 on end # SDIO/MMC Port 2
|
||||
device pci 1f.0 on end # LPC bridge
|
||||
device pci 1f.1 on end # PATA Controller
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ DefinitionBlock(
|
|||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv2", // OEM id
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20090419 // OEM revision
|
||||
)
|
||||
|
|
@ -26,7 +26,7 @@ DefinitionBlock(
|
|||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/sch/acpi/globalnvs.asl>
|
||||
#include <soc/intel/sch/acpi/globalnvs.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
|
@ -36,11 +36,10 @@ DefinitionBlock(
|
|||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sch/acpi/sch.asl>
|
||||
#include <southbridge/intel/sch/acpi/sch.asl>
|
||||
#include <soc/intel/sch/acpi/sch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/sch/acpi/sleepstates.asl>
|
||||
#include <soc/intel/sch/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include <console/console.h>
|
||||
#if 0
|
||||
#include "ram/ramtest.c"
|
||||
#include "southbridge/intel/sch/early_smbus.c"
|
||||
#include "soc/intel/sch/early_smbus.c"
|
||||
#endif
|
||||
|
||||
#define RFID_TEST 0
|
||||
|
|
@ -268,9 +268,9 @@ int selectcard(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#include "northbridge/intel/sch/early_init.c"
|
||||
#include <northbridge/intel/sch/raminit.h>
|
||||
#include "northbridge/intel/sch/raminit.c"
|
||||
#include "soc/intel/sch/early_init.c"
|
||||
#include <soc/intel/sch/raminit.h>
|
||||
#include "soc/intel/sch/raminit.c"
|
||||
|
||||
static void sch_enable_lpc(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,27 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2007-2009 coresystems GmbH
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
config NORTHBRIDGE_INTEL_SCH
|
||||
bool
|
||||
select MMCONF_SUPPORT
|
||||
select LATE_CBMEM_INIT
|
||||
select INTEL_GMA_ACPI
|
||||
|
||||
if NORTHBRIDGE_INTEL_SCH
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
default "8086,8108"
|
||||
endif
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2007-2009 coresystems GmbH
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SCH),y)
|
||||
|
||||
ramstage-y += northbridge.c
|
||||
ramstage-y += gma.c
|
||||
ramstage-y += port_access.c
|
||||
ramstage-y += acpi.c
|
||||
|
||||
endif
|
||||
|
|
@ -1,77 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "hostbridge.asl"
|
||||
|
||||
/* PCI Device Resource Consumption */
|
||||
Device (PDRC)
|
||||
{
|
||||
Name (_HID, EISAID("PNP0C02"))
|
||||
Name (_UID, 1)
|
||||
|
||||
// This does not seem to work correctly yet - set values statically for
|
||||
// now.
|
||||
|
||||
//Name (PDRS, ResourceTemplate() {
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
|
||||
// Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
|
||||
//})
|
||||
|
||||
Name (PDRS, ResourceTemplate() {
|
||||
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
|
||||
Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
|
||||
Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
|
||||
Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
|
||||
Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
|
||||
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
|
||||
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
|
||||
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
|
||||
})
|
||||
|
||||
// Current Resource Settings
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
|
||||
//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
|
||||
//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
|
||||
|
||||
Return(PDRS)
|
||||
}
|
||||
}
|
||||
|
||||
// PCIe graphics port 0:1.0
|
||||
#include "peg.asl"
|
||||
|
||||
// Integrated graphics 0:2.0
|
||||
#include "igd.asl"
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
* 2012 secunet Security Networks AG
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_INTEL_SCH_CHIP_H
|
||||
#define NORTHBRIDGE_INTEL_SCH_CHIP_H
|
||||
|
||||
#include <drivers/intel/gma/i915.h>
|
||||
|
||||
struct northbridge_intel_sch_config {
|
||||
struct i915_gpu_controller_info gfx;
|
||||
};
|
||||
|
||||
#endif /* NORTHBRIDGE_INTEL_SCH_CHIP_H */
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_INTEL_SCH_NVS_H
|
||||
#define NORTHBRIDGE_INTEL_SCH_NVS_H
|
||||
|
||||
typedef struct {
|
||||
u16 osys;
|
||||
u8 smif;
|
||||
u8 prm0;
|
||||
u8 prm1;
|
||||
u8 scif;
|
||||
u8 prm2;
|
||||
u8 prm3;
|
||||
u8 lckf;
|
||||
u8 prm4;
|
||||
u8 prm5;
|
||||
u32 p80d;
|
||||
u8 lids;
|
||||
u8 pwrs;
|
||||
u8 dbgs;
|
||||
u8 linxs;
|
||||
u8 rsvd;
|
||||
u8 actt;
|
||||
u8 psvt;
|
||||
u8 tc1v;
|
||||
u8 tc2v;
|
||||
u8 tspv;
|
||||
u8 crtt;
|
||||
u8 dtse;
|
||||
u8 dts1;
|
||||
u8 dts2;
|
||||
u8 rsvd2;
|
||||
u8 bnum;
|
||||
u8 b0sc, b1sc, b2sc;
|
||||
u8 b0ss, b1ss, b2ss;
|
||||
u8 rsvd3[3];
|
||||
u8 apic;
|
||||
u8 mpen;
|
||||
u8 bten;
|
||||
u8 ppcm;
|
||||
u8 pcp0;
|
||||
u8 pcp1;
|
||||
u8 rsvd4[4];
|
||||
u8 natp;
|
||||
u8 cmap;
|
||||
u8 cmbp;
|
||||
u8 lptp;
|
||||
u8 fdcp;
|
||||
u8 rfdv;
|
||||
u8 hotk;
|
||||
u8 rtcf;
|
||||
u8 util;
|
||||
u8 acin;
|
||||
u8 igds;
|
||||
u8 tlst;
|
||||
u8 cadl;
|
||||
u8 padl;
|
||||
u16 cste;
|
||||
u16 pste;
|
||||
u16 nste;
|
||||
u16 sste;
|
||||
u8 ndid;
|
||||
u32 did1;
|
||||
u32 did2;
|
||||
u32 did3;
|
||||
u32 did4;
|
||||
u32 did5;
|
||||
u8 rsvd5[0xb];
|
||||
u8 brtl;
|
||||
u8 odds;
|
||||
u8 alse;
|
||||
u8 alaf;
|
||||
u8 llow;
|
||||
u8 lhih;
|
||||
u8 rsvd6;
|
||||
u8 emae;
|
||||
u16 emap;
|
||||
u16 emal;
|
||||
u8 rsvd7;
|
||||
u8 mefe;
|
||||
u8 igps;
|
||||
u8 rsvd8[2];
|
||||
u8 tpmp;
|
||||
u8 tpme;
|
||||
u8 rsvd9[8];
|
||||
u8 gtf0[7];
|
||||
u8 gtf2[7];
|
||||
u8 idem;
|
||||
u8 idet;
|
||||
u8 dock;
|
||||
} global_nvs_t;
|
||||
|
||||
#endif /* NORTHBRIDGE_INTEL_SCH_NVS_H */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2007-2010 coresystems GmbH
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
config SOC_INTEL_SCH
|
||||
bool
|
||||
select MMCONF_SUPPORT
|
||||
select LATE_CBMEM_INIT
|
||||
select INTEL_GMA_ACPI
|
||||
select SOUTHBRIDGE_INTEL_COMMON
|
||||
select HAVE_USBDEBUG
|
||||
select HAVE_HARD_RESET
|
||||
select HAVE_SMI_HANDLER
|
||||
|
||||
if SOC_INTEL_SCH
|
||||
|
||||
config VGA_BIOS_ID
|
||||
string
|
||||
default "8086,8108"
|
||||
|
||||
config EHCI_BAR
|
||||
hex
|
||||
default 0xfef00000
|
||||
|
||||
config HAVE_CMC
|
||||
bool "Add a CMC state machine binary"
|
||||
help
|
||||
Select this option to add a CMC state machine binary to
|
||||
the resulting coreboot image.
|
||||
|
||||
Note: Without this binary coreboot will not work
|
||||
|
||||
config CMC_FILE
|
||||
string "Intel CMC path and filename"
|
||||
depends on HAVE_CMC
|
||||
default "cmc.bin"
|
||||
help
|
||||
The path and filename of the file to use as CMC state machine
|
||||
binary.
|
||||
|
||||
config HPET_MIN_TICKS
|
||||
hex
|
||||
default 0x80
|
||||
|
||||
endif
|
||||
|
|
@ -1,19 +1,24 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2010 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2007-2010 coresystems GmbH
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_SCH),y)
|
||||
ifeq ($(CONFIG_SOC_INTEL_SCH),y)
|
||||
|
||||
ramstage-y += northbridge.c
|
||||
ramstage-y += gma.c
|
||||
ramstage-y += port_access.c
|
||||
ramstage-y += acpi.c
|
||||
|
||||
ramstage-y += south.c
|
||||
ramstage-y += audio.c
|
||||
|
|
@ -14,8 +14,69 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Intel i82801G support
|
||||
*/
|
||||
#include "hostbridge.asl"
|
||||
|
||||
/* PCI Device Resource Consumption */
|
||||
Device (PDRC)
|
||||
{
|
||||
Name (_HID, EISAID("PNP0C02"))
|
||||
Name (_UID, 1)
|
||||
|
||||
// This does not seem to work correctly yet - set values statically for
|
||||
// now.
|
||||
|
||||
//Name (PDRS, ResourceTemplate() {
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
|
||||
// Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
|
||||
// Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
|
||||
//})
|
||||
|
||||
Name (PDRS, ResourceTemplate() {
|
||||
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
|
||||
Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
|
||||
Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
|
||||
Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
|
||||
Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
|
||||
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
|
||||
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
|
||||
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
|
||||
})
|
||||
|
||||
// Current Resource Settings
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
|
||||
//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
|
||||
//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
|
||||
|
||||
//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
|
||||
//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
|
||||
|
||||
Return(PDRS)
|
||||
}
|
||||
}
|
||||
|
||||
// PCIe graphics port 0:1.0
|
||||
#include "peg.asl"
|
||||
|
||||
// Integrated graphics 0:2.0
|
||||
#include "igd.asl"
|
||||
|
||||
/* Intel PCH support */
|
||||
|
||||
Scope(\)
|
||||
{
|
||||
|
|
@ -1,7 +1,8 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
* 2012 secunet Security Networks AG
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -13,10 +14,14 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOUTHBRIDGE_INTEL_SCH_CHIP_H
|
||||
#define SOUTHBRIDGE_INTEL_SCH_CHIP_H
|
||||
#ifndef SOC_INTEL_SCH_CHIP_H
|
||||
#define SOC_INTEL_SCH_CHIP_H
|
||||
|
||||
#include <drivers/intel/gma/i915.h>
|
||||
|
||||
struct soc_intel_sch_config {
|
||||
struct i915_gpu_controller_info gfx;
|
||||
|
||||
struct southbridge_intel_sch_config {
|
||||
/**
|
||||
* Interrupt Routing configuration
|
||||
* If bit7 is 1, the interrupt is disabled.
|
||||
|
|
@ -31,4 +36,4 @@ struct southbridge_intel_sch_config {
|
|||
uint8_t pirqh_routing;
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif /* SOC_INTEL_SCH_CHIP_H */
|
||||
|
|
@ -14,7 +14,6 @@
|
|||
*/
|
||||
|
||||
#include "sch.h"
|
||||
#include <southbridge/intel/sch/sch.h>
|
||||
|
||||
#if 0
|
||||
static void sch_set_mtrr(void)
|
||||
|
|
@ -49,7 +49,7 @@ intel_gma_get_controller_info(void)
|
|||
if (!dev) {
|
||||
return NULL;
|
||||
}
|
||||
struct northbridge_intel_sch_config *chip = dev->chip_info;
|
||||
struct soc_intel_sch_config *chip = dev->chip_info;
|
||||
return &chip->gfx;
|
||||
}
|
||||
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
#define PIRQG_ROUT 0x66
|
||||
#define PIRQH_ROUT 0x67
|
||||
|
||||
typedef struct southbridge_intel_sch_config config_t;
|
||||
typedef struct soc_intel_sch_config config_t;
|
||||
|
||||
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
|
||||
* 0x00 - 0000 = Reserved
|
||||
|
|
@ -13,6 +13,9 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOC_INTEL_SCH_NVS_H
|
||||
#define SOC_INTEL_SCH_NVS_H
|
||||
|
||||
typedef struct {
|
||||
/* Miscellaneous */
|
||||
u16 osys; /* 0x00 - Operating System */
|
||||
|
|
@ -133,3 +136,5 @@ typedef struct {
|
|||
} __attribute__((packed)) global_nvs_t;
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t * gnvs);
|
||||
|
||||
#endif /* SOC_INTEL_SCH_NVS_H */
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2009-2010 iWave Systems
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
|
@ -15,12 +15,14 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SCH_PULSBO_H__
|
||||
#define __SCH_PULSBO_H__
|
||||
#ifndef __SCH_POULSBO_H__
|
||||
#define __SCH_POULSBO_H__
|
||||
|
||||
#if !defined(__ASSEMBLER__)
|
||||
int sch_port_access_read(int port, int reg, int bytes);
|
||||
void sch_port_access_write(int port, int reg, int bytes, long data);
|
||||
void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
|
||||
#endif
|
||||
|
||||
/* Southbridge IO BARs */
|
||||
/* TODO Make sure these don't get changed by stage2 */
|
||||
|
|
@ -47,4 +49,21 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
|
|||
/* FIXME: should probably be in southbridge, but is setup in romstage, too */
|
||||
#define CMC_SHADOW 0x3faf0000
|
||||
|
||||
#endif /* __SCH_PULSBO_H__ */
|
||||
#define DEFAULT_PMBASE 0x500
|
||||
|
||||
/* SMBus I/O bits. */
|
||||
#define SMBHSTSTAT 0x0
|
||||
#define SMBHSTCTL 0x2
|
||||
#define SMBHSTCMD 0x3
|
||||
#define SMBXMITADD 0x4
|
||||
#define SMBHSTDAT0 0x5
|
||||
#define SMBHSTDAT1 0x6
|
||||
#define SMBBLKDAT 0x7
|
||||
#define SMBTRNSADD 0x9
|
||||
#define SMBSLVDATA 0xa
|
||||
#define SMLINK_PIN_CTL 0xe
|
||||
#define SMBUS_PIN_CTL 0xf
|
||||
|
||||
#define SMBUS_TIMEOUT (10 * 1000 * 100)
|
||||
|
||||
#endif /* __SCH_POULSBO_H__ */
|
||||
|
|
@ -32,15 +32,15 @@ static void usb_init(struct device *dev)
|
|||
reg32 = pci_read_config32(dev, 0xFC);
|
||||
reg32 |= (1 << 2);
|
||||
pci_write_config32(dev, 0xFC, reg32);
|
||||
pci_write_config8(dev,0xF8,0x86);
|
||||
pci_write_config8(dev,0xF9,0x0F);
|
||||
pci_write_config8(dev,0xFA,0x06);
|
||||
pci_write_config8(dev, 0xF8, 0x86);
|
||||
pci_write_config8(dev, 0xF9, 0x0F);
|
||||
pci_write_config8(dev, 0xFA, 0x06);
|
||||
reg32 = pci_read_config32(dev, 0x4);
|
||||
printk(BIOS_DEBUG, "PCI_COMMAND %x.\n",reg32);
|
||||
printk(BIOS_DEBUG, "PCI_COMMAND %x.\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0x20);
|
||||
printk(BIOS_DEBUG, "PCI_BASE %x.\n",reg32);
|
||||
printk(BIOS_DEBUG, "PCI_BASE %x.\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0xFC);
|
||||
printk(BIOS_DEBUG, "PCI_FD %x.\n",reg32);
|
||||
printk(BIOS_DEBUG, "PCI_FD %x.\n", reg32);
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
|
||||
|
|
@ -29,21 +29,23 @@ static void usb_ehci_init(struct device *dev)
|
|||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_MASTER;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
/*Disable clock gating
|
||||
/* Disable clock gating */
|
||||
#if 0
|
||||
reg32 = pci_read_config32(dev, 0xc0);
|
||||
reg32 |= (1 << 2);
|
||||
pci_write_config32(dev, 0xc0, reg32);*/
|
||||
//pci_write_config32(dev, 0x3c, 0x17);
|
||||
pci_write_config32(dev, 0xc0, reg32);
|
||||
#endif
|
||||
// pci_write_config32(dev, 0x3c, 0x17);
|
||||
reg32 = pci_read_config32(dev, 0xFC);
|
||||
reg32 |= (1 << 28);
|
||||
pci_write_config32(dev, 0xFC, reg32);
|
||||
|
||||
reg32 = pci_read_config32(dev, 0x4);
|
||||
printk(BIOS_DEBUG, "PCI_COMMAND %x.\n",reg32);
|
||||
printk(BIOS_DEBUG, "PCI_COMMAND %x.\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0x20);
|
||||
printk(BIOS_DEBUG, "PCI_BASE %x.\n",reg32);
|
||||
printk(BIOS_DEBUG, "PCI_BASE %x.\n", reg32);
|
||||
reg32 = pci_read_config32(dev, 0xC0);
|
||||
printk(BIOS_DEBUG, "PCI_FD %x.\n",reg32);
|
||||
printk(BIOS_DEBUG, "PCI_FD %x.\n", reg32);
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2010 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
config SOUTHBRIDGE_INTEL_SCH
|
||||
bool
|
||||
select SOUTHBRIDGE_INTEL_COMMON
|
||||
select HAVE_USBDEBUG
|
||||
select HAVE_HARD_RESET
|
||||
select HAVE_SMI_HANDLER
|
||||
|
||||
if SOUTHBRIDGE_INTEL_SCH
|
||||
|
||||
config EHCI_BAR
|
||||
hex
|
||||
default 0xfef00000
|
||||
|
||||
config HAVE_CMC
|
||||
bool "Add a CMC state machine binary"
|
||||
help
|
||||
Select this option to add a CMC state machine binary to
|
||||
the resulting coreboot image.
|
||||
|
||||
Note: Without this binary coreboot will not work
|
||||
|
||||
config CMC_FILE
|
||||
string "Intel CMC path and filename"
|
||||
depends on HAVE_CMC
|
||||
default "cmc.bin"
|
||||
help
|
||||
The path and filename of the file to use as CMC state machine
|
||||
binary.
|
||||
|
||||
config HPET_MIN_TICKS
|
||||
hex
|
||||
default 0x80
|
||||
|
||||
endif
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOUTHBRIDGE_INTEL_SCH_SCH_H
|
||||
#define SOUTHBRIDGE_INTEL_SCH_SCH_H
|
||||
|
||||
#define DEFAULT_PMBASE 0x500
|
||||
|
||||
/* SMBus I/O bits. */
|
||||
#define SMBHSTSTAT 0x0
|
||||
#define SMBHSTCTL 0x2
|
||||
#define SMBHSTCMD 0x3
|
||||
#define SMBXMITADD 0x4
|
||||
#define SMBHSTDAT0 0x5
|
||||
#define SMBHSTDAT1 0x6
|
||||
#define SMBBLKDAT 0x7
|
||||
#define SMBTRNSADD 0x9
|
||||
#define SMBSLVDATA 0xa
|
||||
#define SMLINK_PIN_CTL 0xe
|
||||
#define SMBUS_PIN_CTL 0xf
|
||||
|
||||
#define SMBUS_TIMEOUT (10 * 1000 * 100)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue