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soc/intel/common: Add PMC IPC commands for FIVR control 

Add PMC IPC commands information for FIVR control functionality

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2021-09-24 18:33:38 +05:30 committed by Felix Held
parent ae90f2ebc5
commit 4bb63e81f2
1 changed files with 10 additions and 2 deletions
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12
src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
View File

@ -18,12 +18,20 @@
/* IPC command to control FIVR Configuration */
#define PMC_IPC_CMD_COMMAND_FIVR 0xA3
/* IPC subcommand to read FIVR Register */
#define PMC_IPC_CMD_CMD_ID_FIVR_READ 0x00
/* IPC subcommand to write FIVR Register */
#define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01
/* IPC subcommand to control RFI Control 0 register logic write */
#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00
#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0
/* IPC subcommand to control RFI Control 4 register logic write */
#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01
#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 1
/* IPC subcommand to control EMI Control 0 register logic write */
#define PMC_IPC_SUBCMD_EMI_CTRL0_LOGIC 2
/* IPC subcommand to control FFFC_FAULT_STATUS register logic read */
#define PMC_IPC_SUBCMD_FFFC_FAULT_STATUS 3
/* IPC subcommand to control FFFC_RFI_STATUS register logic read */
#define PMC_IPC_SUBCMD_FFFC_RFI_STATUS 4
#define PMC_IPC_CMD_FIELD(name, val) \
((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT))