GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

change things that make no sense on ultra40. serial output now works! 

Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-10-13 19:58:52 +00:00 committed by Ronald G. Minnich
parent c34e3ab71e
commit 4bb8887ac4
1 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/sunw/ultra40/failover.c
View File

@ -23,6 +23,10 @@
#define SUPERIO_GPIO_IO_BASE 0x400 #define SUPERIO_GPIO_IO_BASE 0x400
#define SUPERIO_COM1_DEV PNP_DEV(0x2e, LPC47B397_SP1)
#define SUPERIO_COM1_IO_BASE 0x3f8
static void sio_setup(void) static void sio_setup(void)
{ {
@ -41,11 +45,15 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1 #if 1
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); lpc47b397_enable_serial(SUPERIO_COM1_DEV, SUPERIO_COM1_IO_BASE);
#if 0
/* what's this?
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf; value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
*/
#endif
#endif #endif
} }