rk3288: Allow board-specific APLL (CPU clock) settings
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -59,7 +59,7 @@ void bootblock_mainboard_init(void)
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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rkclk_configure_cpu(APLL_1800_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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rkclk_configure_cpu(APLL_1800_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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rkclk_configure_cpu(APLL_1800_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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rkclk_configure_cpu(APLL_1800_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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@ -65,7 +65,7 @@ void bootblock_mainboard_init(void)
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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rkclk_configure_cpu(APLL_1392_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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rkclk_configure_cpu(APLL_1800_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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@ -73,10 +73,17 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
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"divisors on line " STRINGIFY(__LINE__));
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/* Keep divisors as low as possible to reduce jitter and power usage. */
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
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static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
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static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
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static const struct pll_div *apll_cfgs[] = {
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[APLL_1800_MHZ] = &apll_1800_cfg,
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[APLL_1392_MHZ] = &apll_1392_cfg,
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};
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/*******************PLL CON0 BITS***************************/
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#define PLL_OD_MSK (0x0F)
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@ -314,13 +321,13 @@ void rkclk_init(void)
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}
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void rkclk_configure_cpu(void)
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void rkclk_configure_cpu(enum apll_frequencies apll_freq)
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{
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/* pll enter slow-mode */
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write32(&cru_ptr->cru_mode_con,
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RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
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rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg);
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rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]);
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/* waiting for pll lock */
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while (1) {
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@ -24,11 +24,15 @@
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#define OSC_HZ (24*MHz)
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#define APLL_HZ (1800*MHz)
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#define GPLL_HZ (594*MHz)
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#define CPLL_HZ (384*MHz)
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#define NPLL_HZ (384*MHz)
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enum apll_frequencies {
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APLL_1800_MHZ,
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APLL_1392_MHZ,
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};
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/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */
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#define PD_BUS_ACLK_HZ (297000*KHz)
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#define PD_BUS_HCLK_HZ (148500*KHz)
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@ -44,7 +48,7 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
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void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
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void rkclk_configure_ddr(unsigned int hz);
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void rkclk_configure_i2s(unsigned int hz);
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void rkclk_configure_cpu(void);
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void rkclk_configure_cpu(enum apll_frequencies apll_freq);
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void rkclk_configure_crypto(unsigned int hz);
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void rkclk_configure_tsadc(unsigned int hz);
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void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
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