lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
LynxPoint-LP has a lot of GPEs and the "default" set has been moved to register 4 starting at bit offset 96. This means that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP but still bit 13 in LPT-H. suspend on falco and wake from usb 4 | 2013-06-19 10:49:17 | ACPI Enter | S3 5 | 2013-06-19 10:49:22 | ACPI Wake | S3 6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0 Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59265 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4253 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
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@ -27,10 +27,15 @@ Device (HDEF)
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{
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Name (_ADR, 0x001b0000)
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// Power Resources for Wake
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Name (_PRW, Package(){
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13, // Bit 13 of GPE
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4 // Can wake from S4 state.
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})
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Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
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Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
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Method (_PRW, 0) { // Power Resources for Wake
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If (\ISLP ()) {
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Return (PRWL)
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} Else {
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Return (PRWH)
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}
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}
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}
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@ -27,7 +27,16 @@ Device (EHCI)
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{
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Name(_ADR, 0x001d0000)
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Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
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Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
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Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
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Method (_PRW, 0) { // Power Resources for Wake
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If (\ISLP ()) {
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Return (PRWL)
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} Else {
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Return (PRWH)
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}
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}
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// Leave USB ports on for to allow Wake from USB
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@ -61,7 +70,16 @@ Device (XHCI)
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{
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Name(_ADR, 0x00140000)
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Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
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Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
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Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
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Method (_PRW, 0) { // Power Resources for Wake
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If (\ISLP ()) {
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Return (PRWL)
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} Else {
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Return (PRWH)
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}
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}
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// Leave USB ports on for to allow Wake from USB
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