soc/amd/cezanne: add common SMBus code to build

Since the IOAPIC in the FCH gets set up in the SMBus code, also select
IOAPIC in Kconfig.

Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/Kconfig

@@ -13,11 +13,13 @@ config SOC_SPECIFIC_OPTIONS
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select IOAPIC
 	select RESET_VECTOR_IN_RAM
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
 
 config EARLY_RESERVED_DRAM_BASE

src/soc/amd/cezanne/include/soc/iomap.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_IOMAP_H
+#define AMD_CEZANNE_IOMAP_H
+
+/* I/O Ranges */
+#define SMB_BASE_ADDR			0xb00
+
+#endif /* AMD_CEZANNE_IOMAP_H */

src/soc/amd/cezanne/include/soc/southbridge.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_SOUTHBRIDGE_H
+#define AMD_CEZANNE_SOUTHBRIDGE_H
+
+#include <soc/iomap.h>
+
+#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */