arm64: xcompile: Add support for A53 erratum 843419

This patch adds support to enable a linker workaround to a hardware
erratum on some early Cortex-A53 revisions. Since the linker option was
added very recently, we use xcompile to test whether the toolchain
supports it first. It is also guarded by a Kconfig since only a few
ARM64 SoCs will need this and it incurs a performance penalty.

BRANCH=none
BUG=none
TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared
in verbose make output accordingly.

Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7
Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294745
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11403
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

payloads/libpayload/arch/arm64/Kconfig

@@ -33,6 +33,14 @@ config ARCH_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select LITTLE_ENDIAN
 
+config ARM64_A53_ERRATUM_843419
+	bool "Enable Cortex-A53 erratum 843419 linker workaround"
+	default n
+	help
+	  Some early Cortex-A53 revisions had a hardware bug that results in
+	  incorrect address calculations in rare cases. This option enables a
+	  linker workaround to avoid those cases if your toolchain supports it.
+
 config DMA_LIM_EXCL
 	hex "DMA address limit(exclusive) in MiB units"
 	default 0x1000

payloads/libpayload/bin/lpgcc

@@ -181,6 +181,12 @@ else
 	    echo "Could not find head.o"
 	    exit 1
     fi
+
+    if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config &&
+       grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then
+            _LDFLAGS+=" -Wl,--fix-cortex-a53-843419"
+    fi
+
     if [ $DEBUGME -eq 1 ]; then
 	echo "$DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
     fi

src/arch/arm64/Kconfig

@@ -55,3 +55,12 @@ config ARM64_SECURE_OS_FILE
 	depends on ARM64_USE_SECURE_OS
 	help
 	  Secure OS binary file.
+
+config ARM64_A53_ERRATUM_843419
+	bool
+	default n
+	help
+	  Some early Cortex-A53 revisions had a hardware bug that results in
+	  incorrect address calculations in rare cases. This option enables a
+	  linker workaround to avoid those cases if your toolchain supports it.
+	  Should be selected automatically by SoCs that are affected.

util/xcompile/xcompile

@@ -87,6 +87,18 @@ testcc() {
 	$1 -nostdlib -Werror $2 -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
 }
 
+testld() {
+	local gcc="$1"
+	local cflags="$2"
+	local ld="$3"
+	local ldflags="$4"
+	local tmp_o="$TMPFILE.o"
+	local tmp_elf="$TMPFILE.elf"
+	rm -f "$tmp_elf"
+	testcc $1 $2 &&
+	$3 -nostdlib -static $4 -o "$tmp_elf" "$tmp_o" >/dev/null 2>&1
+}
+
 testas() {
 	local gccprefix="$1"
 	local twidth="$2"
@@ -163,6 +175,11 @@ detect_special_flags() {
 		;;
 	x64)
 		;;
+	arm64)
+		testld "$GCC" "$CFLAGS_GCC" "${GCCPREFIX}ld${LINKER_SUFFIX}" \
+		  "$LDFLAGS --fix-cortex-a53-843419" && \
+		  LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419"
+		;;
 	mipsel)
 		testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \
 		  CFLAGS_GCC+=" -mno-abicalls -fno-pic"
@@ -203,6 +220,9 @@ endif
 CPP_${TARCH}:=${GCCPREFIX}cpp
 AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS}
 LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS}
+ifeq (\$(CONFIG_ARM64_A53_ERRATUM_843419)\$(CONFIG_LP_ARM64_A53_ERRATUM_843419),y)
+LD_${TARCH}+=${LDFLAGS_ARM64_A53_ERRATUM_843419}
+endif
 NM_${TARCH}:=${GCCPREFIX}nm
 OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy
 OBJDUMP_${TARCH}:=${GCCPREFIX}objdump