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sb/amd/pi: Fix some white spaces issues 

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I90278683bc22d87364453f316c05afe4cd96b383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas 2022-07-16 09:51:03 +02:00 committed by Martin L Roth
parent 7d89264cdf
commit 4c15211a78
5 changed files with 10 additions and 10 deletions
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2
src/southbridge/amd/pi/hudson/amd_pci_int_types.h
View File

@ -17,7 +17,7 @@ const char *intr_types[] = {
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
[0x62] = "GPIO\t",
[0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
[0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",
#endif
};

4
src/southbridge/amd/pi/hudson/early_setup.c
View File

@ -187,7 +187,7 @@ void hudson_clk_output_48Mhz(void)
ctrl = misc_read32(FCH_MISC_REG40);
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
ctrl &= (u32)~(1<<2);
ctrl &= (u32)~(1 << 2);
misc_write32(FCH_MISC_REG40, ctrl);
}
@ -198,7 +198,7 @@ static uintptr_t hudson_spibase(void)
u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)
& 0xfffffff0;
if (!base){
if (!base) {
base = SPI_BASE_ADDRESS;
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base
| SPI_ROM_ENABLE);

2
src/southbridge/amd/pi/hudson/fchec.h
View File

@ -8,7 +8,7 @@
#include <AGESA.h>
#include "FchCommonCfg.h"
extern VOID FchECfancontrolservice (IN VOID *FchDataPtr);
extern VOID FchECfancontrolservice(IN VOID *FchDataPtr);
void agesawrapper_fchecfancontrolservice(void);
#endif

6
src/southbridge/amd/pi/hudson/lpc.c
View File

@ -69,10 +69,10 @@ static void lpc_init(struct device *dev)
cmos_init(0);
/* Initialize i8259 pic */
setup_i8259 ();
setup_i8259();
/* Initialize i8254 timers */
setup_i8254 ();
setup_i8254();
/* Set up SERIRQ, enable continuous mode */
byte = (BIT(4) | BIT(7));
@ -255,7 +255,7 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev)
default:
rsize = 0;
/* try AGESA allocated region in region 0 */
if ((var_num > 0) && ((base >=reg_var[0]) &&
if ((var_num > 0) && ((base >= reg_var[0]) &&
((base + res->size) <= (reg_var[0] + reg_size[0]))))
rsize = reg_size[0];
}

6
src/southbridge/amd/pi/hudson/reset.c
View File

@ -8,9 +8,9 @@
#include <reset.h>
#define HT_INIT_CONTROL 0x6c
#define HTIC_ColdR_Detect (1<<4)
#define HTIC_BIOSR_Detect (1<<5)
#define HTIC_INIT_Detect (1<<6)
#define HTIC_ColdR_Detect (1 << 4)
#define HTIC_BIOSR_Detect (1 << 5)
#define HTIC_INIT_Detect (1 << 6)
void cf9_reset_prepare(void)
{