Supermicro H8QGI: set up right frequency limits for memory controller
According to BKDG: "Memory controller (MCT) and DRAM controllers (DCTs) additions: • Support for 933 MHz (1866 MT/s) MEMCLK frequency." Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
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#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
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#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
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#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
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#define BLDCFG_ONLINE_SPARE FALSE
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#define BLDCFG_BANK_SWIZZLE TRUE
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#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
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#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY
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#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
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#define BLDCFG_DQS_TRAINING_CONTROL TRUE
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#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
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#define BLDCFG_USE_BURST_MODE FALSE
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