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Supermicro H8QGI: set up right frequency limits for memory controller 

According to BKDG:
"Memory controller (MCT) and DRAM controllers (DCTs) additions:
• Support for 933 MHz (1866 MT/s) MEMCLK frequency."

Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2589
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Konstantin Aladyshev 2013-03-06 21:39:40 +04:00 committed by Marc Jones
parent 7fcbbb09fd
commit 4c1e906e36
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/supermicro/h8qgi/buildOpts.c
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@ -94,7 +94,7 @@
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
@ -110,7 +110,7 @@
#define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY #define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE #define BLDCFG_USE_BURST_MODE FALSE