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Make AMD Fam10h CPU microcode updates optional in Expert mode 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran 2011-02-26 23:29:44 +00:00 committed by Peter Stuge
parent 837403dddf
commit 4c28a6f018
18 changed files with 125 additions and 2 deletions
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32
src/cpu/amd/model_10xxx/Kconfig
View File

@ -50,3 +50,35 @@ config SET_FIDVID_CORE_RANGE
endif
endif
config UPDATE_CPU_MICROCODE
bool
default y
config UPDATE_CPU_MICROCODE
bool "Update CPU microcode"
default y
depends on EXPERT && CPU_AMD_MODEL_10XXX
help
Select this to apply patches to the CPU microcode provided by
AMD without source, and distributed with coreboot, to address
issues in the CPU post production.
Microcode updates distributed with coreboot are not necessarily
the latest version available from AMD. Updates are only applied
if they are newer than the microcode already in your CPU.
Unselect this to let Fam10h CPUs run with microcode as shipped
from factory. No binary microcode patches will be included in the
coreboot image in that case, which can help with creating an image
for which complete source code is available, which in turn might
simplify license compliance.
Microcode updates intend to solve issues that have been discovered
after CPU production. The common case is that systems work as
intended with updated microcode, but we have also seen cases where
issues were solved by not applying the microcode updates.
Note that some operating system include these same microcode
patches, so you may need to also disable microcode updates in
your operating system in order for this option to matter.

3
src/cpu/amd/model_10xxx/Makefile.inc
View File

@ -1,5 +1,4 @@
# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_10xxx_init.c
ramstage-y += update_microcode.c
ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
ramstage-y += apic_timer.c
ramstage-y += processor_name.c

2
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -325,7 +325,9 @@ static u32 init_cpus(u32 cpu_init_detectedx)
* This happens after HTinit.
* The BSP runs this code in it's own path.
*/
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(cpuid_eax(1));
#endif
cpuSetAMDMSR();
#if CONFIG_SET_FIDVID

6
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -66,7 +66,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -132,7 +136,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -66,7 +66,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/early_setup.c"
@ -125,7 +129,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -87,7 +87,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -227,7 +231,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -65,7 +65,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -124,7 +128,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -65,7 +65,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -125,7 +129,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -65,7 +65,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -125,7 +129,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -61,7 +61,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -121,7 +125,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -65,7 +65,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -123,7 +127,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -82,7 +82,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -136,7 +140,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -67,7 +67,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -126,7 +130,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -72,7 +72,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
@ -131,7 +135,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -76,7 +76,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -153,7 +157,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -68,7 +68,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -145,7 +149,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -74,7 +74,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -197,7 +201,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();

6
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -77,7 +77,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#if CONFIG_UPDATE_CPU_MICROCODE
#include "cpu/amd/model_10xxx/update_microcode.c"
#endif
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@ -153,7 +157,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();