From 4c3851afbf8ec0b334d9a899dd436700ed92e89a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 17 Nov 2020 14:17:06 -0600 Subject: [PATCH] mb/purism/librem_cnl: Add new board/variant Librem 14 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the CometLake-U based Librem 14 laptop. Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_cnl/Kconfig | 6 +- src/mainboard/purism/librem_cnl/Kconfig.name | 11 + src/mainboard/purism/librem_cnl/Makefile.inc | 1 + .../variants/librem_14/board_info.txt | 8 + .../librem_cnl/variants/librem_14/data.vbt | Bin 0 -> 4608 bytes .../variants/librem_14/devicetree.cb | 284 +++++++++ .../variants/librem_14/gma-mainboard.ads | 19 + .../librem_cnl/variants/librem_14/gpio.c | 600 ++++++++++++++++++ .../librem_cnl/variants/librem_14/hda_verb.c | 65 ++ .../librem_14/include/variant/acpi/gpe.asl | 11 + .../librem_14/include/variant/acpi/sleep.asl | 11 + .../include/variant/acpi/variant.asl | 24 + .../librem_cnl/variants/librem_14/variant.c | 8 + 13 files changed, 1047 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/data.vbt create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/gma-mainboard.ads create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/variant.c diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 919240244f..eeb4d3b9db 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -21,15 +21,18 @@ config MAINBOARD_DIR config MAINBOARD_FAMILY string default "Librem Mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 + default "Librem 14" if BOARD_PURISM_LIBREM_14 config MAINBOARD_PART_NUMBER string default "Librem Mini" if BOARD_PURISM_LIBREM_MINI default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2 + default "Librem 14" if BOARD_PURISM_LIBREM_14 config VARIANT_DIR string default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 + default "librem_14" if BOARD_PURISM_LIBREM_14 config DEVICETREE string @@ -39,6 +42,7 @@ config CBFS_SIZE hex default 0x800000 if BOARD_PURISM_LIBREM_MINI default 0xA00000 if BOARD_PURISM_LIBREM_MINI_V2 + default 0x900000 if BOARD_PURISM_LIBREM_14 config DIMM_MAX int @@ -51,7 +55,7 @@ config DIMM_SPD_SIZE config VGA_BIOS_ID string default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI - default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2 + default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2 || BOARD_PURISM_LIBREM_14 config PXE_ROM_ID string diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name index 1d10e791f1..5a2b3c2c1e 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig.name +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -7,3 +7,14 @@ config BOARD_PURISM_LIBREM_MINI_V2 bool "Librem Mini v2" select BOARD_PURISM_BASEBOARD_LIBREM_CNL select SOC_INTEL_COMETLAKE_1 + +config BOARD_PURISM_LIBREM_14 + bool "Librem 14" + select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select DRIVERS_I2C_HID + select EC_SYSTEM76_EC + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select SOC_INTEL_COMETLAKE_1 + select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc index c8cfa2212e..131385e255 100644 --- a/src/mainboard/purism/librem_cnl/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/Makefile.inc @@ -5,6 +5,7 @@ romstage-y += variants/$(VARIANT_DIR)/variant.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt b/src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt new file mode 100644 index 0000000000..d9cc69d93d --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem 14 +Category: laptop +Release year: 2021 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/data.vbt b/src/mainboard/purism/librem_cnl/variants/librem_14/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..e1943f832e5e05fbb0d0fa9faa86707533b616aa GIT binary patch literal 4608 zcmeHKUu;ul6hF7Oe{R2fZ+Ck~q^md&e**1b<90yBIpXcw&6O3}tz#L{WCdDqp|H6> zIt*qtS(FDQeNcl2WiLeKMSL>8;TwsGl9=F=5fc*>UnKHkKdOFdjJZNyz-%jnV)R9bQhZ3>=*ic6*9q+-P;W3!- zU%v#9=ePzbqG^%j!HGgK)E6e$6mA>YJzOlTPZY-YPmGLWCZ5FDo;`(PVQkk#A&=RC z=VEAJ%B*8@xR}T7lLvMe#@dj8G#ZVOjV&8CB1YD?(!UnjM5@*niMDNeT4ssPczRnV znTqu%)7vrKhlyl1md$o<>qzayOkcV?*^%t;OvtPnMto%S(Ae<47bh?j4`VCM(QJa6 zE@OOTY_tVq#Ul0@W5%(sFkTpYxsY#>nE`SJ1Sbc;xu8x54*qHdGJv3ifFLN~)WM11 zR6s}26+i_904IPBfB=f&gaVE&oP%s@1aJoo%N!9rZ|b@+*d{`Q^EpryLG@ZD4^3}s z3Wt_LJ(|uQw#ptx6FcaE6OcngF$rm)g%-7kk+3G!IJ6WRh_v_T_at1aI7&b}K~&;w>9-^(PBN?B>xnC{&8YrPHs#G3!O{#~j^e*v2`^+*kmK^|<6EY7|!2I;8*`!KyNog9E zd<5>G^~lpcH)f&yH=hKJli_iRKj&d^&U1x3Qvcu7j5Sjh`Lot_KGm%LqxR7X+}#Q+ z>xT2*QW-Bip$NGZ)^8i{&GO_6l(Pi2tfc6unLwy4l-taC79>%O-|Nk zLWH{N)qd0OtDR6I_+Y%+wG})?Wa;5|fZxaPZKj@J>{Eu{GW93Meq-nt)s-S^7BMTT z1(A)2_^zmaEV9o<{9aUl71nO?9~!ze zFonHAMOSV>;L5JMK=@?+)P>&QYJKq7yboO2Z6fII(>3_e{j9F-KHaM8XXX*y zR+S_TxN2F+y~_tq^+Kc8RkruSSjn<^zmhApti$1!@@y{HsB38N1?{G@Y*w*S$x}-d zq4v`3=;@V&&}768KnSj~S<6VXu9+J0;e+t(x!#!-TIT(wRRkW)5?a#TwIFCs`q|t} zUJLYEHKXAJPw7Z>uQ_QV$QFVNYlz}f5N0#DRFky$d=zDRAIXQ3XS10PMv~t?s~v5n zz)PE(^}*)(z2KqF@`1j77Jo0oI^;@FpHme7ybpAc8a|}DGDDeN2MfjRyABlo2OTTG zJGE Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c new file mode 100644 index 0000000000..49c6b8a767 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c @@ -0,0 +1,600 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../../variant.h" + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - RCIN# */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - TPM_SPI_PIRQ# */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + /* GPP_A11 - NC */ + PAD_NC(GPP_A11, UP_20K), + + /* GPP_A12 - NC */ + PAD_NC(GPP_A12, UP_20K), + + /* GPP_A13 - NC */ + PAD_NC(GPP_A13, NONE), + + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + /* GPP_A15 - NC */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - NC */ + PAD_NC(GPP_A16, UP_20K), + + /* GPP_A17 - NC */ + PAD_NC(GPP_A17, NONE), + + /* GPP_A18 - NC */ + PAD_NC(GPP_A18, NONE), + + /* GPP_A19 - NC */ + PAD_NC(GPP_A19, NONE), + + /* GPP_A20 - NC */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - NC */ + PAD_NC(GPP_A21, UP_20K), + + /* GPP_A22 - NC */ + PAD_NC(GPP_A22, UP_20K), + + /* GPP_A23 - NC */ + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), + + /* GPP_B3 - NC */ + PAD_NC(GPP_B3, NONE), + + /* GPP_B4 - NC */ + PAD_NC(GPP_B4, UP_20K), + + /* GPP_B5 - SRCCLKREQ0# / SSD1 */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* GPP_B6 - SRCCLKREQ1# / SSD0 */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + + /* GPP_B8 - SRCCLKREQ2# / WIFI */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + + /* GPP_B8 - SRCCLKREQ3# / LAN */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + + /* GPP_B9 - NC */ + PAD_NC(GPP_B9, UP_20K), + + /* GPP_B10 - NC */ + PAD_NC(GPP_B10, UP_20K), + + /* GPP_B11 - NC */ + PAD_NC(GPP_B11, NONE), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - NC */ + PAD_NC(GPP_B14, NONE), + + /* GPP_B15 - NC */ + PAD_NC(GPP_B15, NONE), + + /* GPP_B16 - LAN_RST */ + PAD_CFG_GPO(GPP_B16, 0, PLTRST), + + /* GPP_B17 - WLAN_PCIE_RST */ + PAD_CFG_GPO(GPP_B17, 0, PLTRST), + + /* GPP_B18 - NC */ + PAD_NC(GPP_B18, NONE), + + /* GPP_B19 - USB3_P1_PWREN */ + PAD_CFG_GPO(GPP_B19, 1, PLTRST), + + /* GPP_B20 - TP_INT# + * + * Due to interrupts failing to trigger when correctly configured + * active-low as PAD_CFG_GPI_APIC_LOW(GPP_B20, NONE, PLTRST), + * must configure instead as active-high: + */ + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, LEVEL, ACPI), + + /* GPP_B21 - NC */ + PAD_NC(GPP_B21, UP_20K), + + /* GPP_B22 - NC */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - NC */ + PAD_NC(GPP_B23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - NC */ + PAD_NC(GPP_G0, NONE), + + /* GPP_G1 - NC */ + PAD_NC(GPP_G1, NONE), + + /* GPP_G2 - NC */ + PAD_NC(GPP_G2, NONE), + + /* GPP_G3 - NC */ + PAD_NC(GPP_G3, NONE), + + /* GPP_G4 - NC */ + PAD_NC(GPP_G4, NONE), + + /* GPP_G5 - NC */ + PAD_NC(GPP_G5, UP_20K), + + /* GPP_G6 - NC */ + PAD_NC(GPP_G6, NONE), + + /* GPP_G7 - NC */ + PAD_NC(GPP_G7, DN_20K), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - NC */ + PAD_NC(GPP_D0, UP_20K), + + /* GPP_D1 - NC */ + PAD_NC(GPP_D1, UP_20K), + + /* GPP_D2 - NC */ + PAD_NC(GPP_D2, UP_20K), + + /* GPP_D3 - NC */ + PAD_NC(GPP_D3, UP_20K), + + /* GPP_D4 - NC */ + PAD_NC(GPP_D4, UP_20K), + + /* GPP_D5 - ISH_I2C0_SDA */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - ISH_I2C0_SCL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - PCH_NVME_RST */ + PAD_CFG_GPO(GPP_D7, 1, PLTRST), + + /* GPP_D8 - PCH_NVME_RST1 */ + PAD_CFG_GPO(GPP_D8, 1, PLTRST), + + /* GPP_D9 - TP_RST */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + + /* GPP_D10 - NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - NC */ + PAD_NC(GPP_D11, UP_20K), + + /* GPP_D12 - NC */ + PAD_NC(GPP_D12, UP_20K), + + /* GPP_D13 - NC */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - NC */ + PAD_NC(GPP_D14, UP_20K), + + /* GPP_D15 - NC */ + PAD_NC(GPP_D15, UP_20K), + + /* GPP_D16 - NC */ + PAD_NC(GPP_D16, UP_20K), + + /* GPP_D17 - DMIC_CLK1 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + + /* GPP_D18 - DMIC_DATA1 */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* GPP_D19 - DMIC_CLK0 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* GPP_D20 - DMIC_DATA0 */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* GPP_D21 - NC */ + PAD_NC(GPP_D21, UP_20K), + + /* GPP_D22 - NC */ + PAD_NC(GPP_D22, UP_20K), + + /* GPP_D23 - NC */ + PAD_NC(GPP_D23, UP_20K), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - NC */ + PAD_NC(GPP_F0, NONE), + + /* GPP_F1 - NC */ + PAD_NC(GPP_F1, UP_20K), + + /* GPP_F2 - NC */ + PAD_NC(GPP_F2, UP_20K), + + /* GPP_F3 - NC */ + PAD_NC(GPP_F3, UP_20K), + + /* GPP_F4 - NC */ + PAD_NC(GPP_F4, UP_20K), + + /* GPP_F5 - NC */ + PAD_NC(GPP_F5, UP_20K), + + /* GPP_F6 - NC */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - NC */ + PAD_NC(GPP_F7, NONE), + + /* GPP_F8 - NC */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - NC */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - NC */ + PAD_NC(GPP_F10, UP_20K), + + /* GPP_F11 - NC */ + PAD_NC(GPP_F11, UP_20K), + + /* GPP_F12 - NC */ + PAD_NC(GPP_F12, UP_20K), + + /* GPP_F13 - NC */ + PAD_NC(GPP_F13, UP_20K), + + /* GPP_F14 - NC */ + PAD_NC(GPP_F14, UP_20K), + + /* GPP_F15 - NC */ + PAD_NC(GPP_F15, UP_20K), + + /* GPP_F16 - NC */ + PAD_NC(GPP_F16, UP_20K), + + /* GPP_F17 - NC */ + PAD_NC(GPP_F17, UP_20K), + + /* GPP_F18 - NC */ + PAD_NC(GPP_F18, UP_20K), + + /* GPP_F19 - NC */ + PAD_NC(GPP_F19, UP_20K), + + /* GPP_F20 - NC */ + PAD_NC(GPP_F20, UP_20K), + + /* GPP_F21 - NC */ + PAD_NC(GPP_F21, UP_20K), + + /* GPP_F22 - NC */ + PAD_NC(GPP_F22, UP_20K), + + /* GPP_F23 - NC */ + PAD_NC(GPP_F23, UP_20K), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - M.2_BT_PCMCLK */ + PAD_NC(GPP_H0, UP_20K), + + /* GPP_H1 - M.2_BT_PCMSYNC */ + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + + /* GPP_H2 - M.2_BT_PCMOUT */ + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + + /* GPP_H3 - M.2_BT_PCMIN */ + PAD_CFG_GPO(GPP_H3, 1, PLTRST), + + /* GPP_H4 - NC */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - NC */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - NC */ + PAD_NC(GPP_H6, UP_20K), + + /* GPP_H7 - NC */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - NC */ + PAD_NC(GPP_H8, NONE), + + /* GPP_H9 - NC */ + PAD_NC(GPP_H9, NONE), + + /* GPP_H10 - NC */ + PAD_NC(GPP_H10, NONE), + + /* GPP_H11 - NC */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - NC */ + PAD_NC(GPP_H12, UP_20K), + + /* GPP_H13 - NC */ + PAD_NC(GPP_H13, UP_20K), + + /* GPP_H14 - NC */ + PAD_NC(GPP_H14, UP_20K), + + /* GPP_H15 - NC */ + PAD_NC(GPP_H15, UP_20K), + + /* GPP_H16 - NC */ + PAD_NC(GPP_H16, UP_20K), + + /* GPP_H17 - NC */ + PAD_NC(GPP_H17, NONE), + + /* GPP_H18 - CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - NC */ + PAD_NC(GPP_H19, UP_20K), + + /* GPP_H20 - NC */ + PAD_NC(GPP_H20, UP_20K), + + /* GPP_H21 - NC */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - NC */ + PAD_NC(GPP_H22, UP_20K), + + /* GPP_H23 - NC */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + + /* GPD7 - NC */ + PAD_NC(GPD7, NONE), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + + /* GPD11 - LANPHYPC */ + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - NC */ + PAD_NC(GPP_C2, NONE), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - NC */ + PAD_NC(GPP_C5, NONE), + + /* GPP_C6 - NC */ + PAD_NC(GPP_C6, NONE), + + /* GPP_C7 - NC */ + PAD_NC(GPP_C7, NONE), + + /* GPP_C8 - NC */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - NC */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - NC */ + PAD_NC(GPP_C10, UP_20K), + + /* GPP_C11 - NC */ + PAD_NC(GPP_C11, UP_20K), + + /* GPP_C12 - NC */ + PAD_NC(GPP_C12, UP_20K), + + /* GPP_C13 - NC */ + PAD_NC(GPP_C13, UP_20K), + + /* GPP_C14 - NC */ + PAD_NC(GPP_C14, UP_20K), + + /* GPP_C15 - NC */ + PAD_NC(GPP_C15, UP_20K), + + /* GPP_C16 - I2C0_SDA - TP */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + + /* GPP_C17 - I2C0_SCL - TP */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + + /* GPP_C18 - NC */ + PAD_NC(GPP_C18, UP_20K), + + /* GPP_C19 - NC */ + PAD_NC(GPP_C19, UP_20K), + + /* GPP_C20 - NC */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - NC */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - NC */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - NC */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - NC */ + PAD_NC(GPP_E0, UP_20K), + + /* GPP_E1 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + + /* GPP_E2 - SATAXPCIE2 */ + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + + /* GPP_E3 - NC */ + PAD_NC(GPP_E3, NONE), + + /* GPP_E4 - SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), + + /* GPP_E5 - SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + + /* GPP_E6 - NC */ + PAD_NC(GPP_E6, UP_20K), + + /* GPP_E7 - NC */ + PAD_NC(GPP_E7, NONE), + + /* GPP_E8 - NC */ + PAD_NC(GPP_E8, UP_20K), + + /* GPP_E9 - USB2_OC0# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + /* GPP_E10 - USB2_OC1# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* GPP_E11 - USB2_OC2# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + + /* GPP_E12 - NC */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - DDPB_HPD0 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* GPP_E14 - DDPC_HPD1 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - SMC_EXTSMI# */ + PAD_CFG_GPI_SCI_LOW(GPP_E15, UP_20K, PLTRST, LEVEL), + + /* GPP_E16 - SMC_RUNTIME_SCI# */ + PAD_CFG_GPI_SCI_LOW(GPP_E16, UP_20K, PLTRST, LEVEL), + + /* GPP_E17 - EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* GPP_E18 - NC */ + PAD_NC(GPP_E18, UP_20K), + + /* GPP_E19 - NC */ + PAD_NC(GPP_E19, NONE), + + /* GPP_E20 - NC */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - NC */ + PAD_NC(GPP_E21, NONE), + + /* GPP_E22 - NC */ + PAD_NC(GPP_E22, UP_20K), + + /* GPP_E23 - NC */ + PAD_NC(GPP_E23, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c new file mode 100644 index 0000000000..97422ef317 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0256, /* Codec Vendor/Device ID: Realtek ALC256 */ + 0x1b50580a, /* Subsystem ID */ + 12, /* Number of entries */ + + AZALIA_SUBVENDOR(0, 0x1b50580a), + + /* Widget node 0x01 */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), /* Front digital mic */ + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Internal speakers */ + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x19, 0x04a11030), /* Jack analog mic */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), /* Jack analog out */ + + /* Hidden SW reset */ + 0x0205001a, + 0x0204c003, + 0x0205001a, + 0x02048003, + + /* Class D power on reset control */ + 0x0205003c, + 0x02040354, + 0x0205003c, + 0x02040314, + + /* LDO3 output set to 1.2V */ + 0x0205001b, + 0x02040a4b, + 0x02050019, + 0x02040e12, + + /* SPK power */ + 0x02050038, + 0x02046901, + 0x02050007, + 0x02040200, + + 0x8086280b, /* Codec Vendor/Device ID: Intel CometPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl new file mode 100644 index 0000000000..611643b54a --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_E15 SWI +Method (_L49, 0, Serialized) { + Debug = Concatenate("GPE _L49: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..48c50e075e --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl new file mode 100644 index 0000000000..def6ee0b8e --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SWI 0x49 /* GPP_E15 */ +#define EC_GPE_SCI 0x50 /* GPP_E16 */ +#define EC_COLOR_KEYBOARD 0 +#include + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} + +Scope (\_SB.PCI0) +{ + #include +} + +Scope (\_SB.PCI0.LPCB) +{ + #include +} diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/variant.c b/src/mainboard/purism/librem_cnl/variants/librem_14/variant.c new file mode 100644 index 0000000000..33f5b6a5ef --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../../variant.h" + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg) +{ + /* No SATA HSIO adjustments needed currently */ +}