cpu/via/nano: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I6d9771e97619c3775f8325daf4b8453cd51d6571 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
parent
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4c38ed3c38
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@ -6,7 +6,6 @@ subdirs-y += amd
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subdirs-y += armltd
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subdirs-y += intel
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subdirs-y += ti
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subdirs-y += via
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subdirs-$(CONFIG_ARCH_X86) += x86
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subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
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@ -1 +0,0 @@
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source src/cpu/via/nano/Kconfig
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@ -1 +0,0 @@
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subdirs-$(CONFIG_CPU_VIA_NANO) += nano
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@ -1,227 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <console/post_codes.h>
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase CONFIG_DCACHE_RAM_BASE
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/* Save the BIST result. */
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movl %eax, %ebp
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CacheAsRam:
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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invd
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/* Set the default memory type and enable fixed and variable MTRRs. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %edx, %edx
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movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
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wrmsr
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/* Clear all MTRRs. */
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xorl %edx, %edx
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movl $all_mtrr_msrs, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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all_mtrr_msrs:
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/* fixed MTRR MSRs */
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.long MTRR_FIX_64K_00000
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.long MTRR_FIX_16K_80000
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.long MTRR_FIX_16K_A0000
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.long MTRR_FIX_4K_C0000
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.long MTRR_FIX_4K_C8000
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.long MTRR_FIX_4K_D0000
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.long MTRR_FIX_4K_D8000
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.long MTRR_FIX_4K_E0000
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.long MTRR_FIX_4K_E8000
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.long MTRR_FIX_4K_F0000
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.long MTRR_FIX_4K_F8000
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/* var MTRR MSRs */
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.long MTRR_PHYS_BASE(0)
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.long MTRR_PHYS_MASK(0)
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.long MTRR_PHYS_BASE(1)
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.long MTRR_PHYS_MASK(1)
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.long MTRR_PHYS_BASE(2)
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.long MTRR_PHYS_MASK(2)
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.long MTRR_PHYS_BASE(3)
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.long MTRR_PHYS_MASK(3)
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.long MTRR_PHYS_BASE(4)
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.long MTRR_PHYS_MASK(4)
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.long MTRR_PHYS_BASE(5)
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.long MTRR_PHYS_MASK(5)
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.long MTRR_PHYS_BASE(6)
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.long MTRR_PHYS_MASK(6)
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.long MTRR_PHYS_BASE(7)
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.long MTRR_PHYS_MASK(7)
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.long 0x000 /* NULL, end of table */
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clear_fixed_var_mtrr_out:
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movl $MTRR_PHYS_BASE(0), %ecx
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xorl %edx, %edx
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movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $MTRR_PHYS_MASK(0), %ecx
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/* This assumes we never access addresses above 2^36 in CAR. */
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movl $0x0000000f, %edx
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movl $(~(CacheSize - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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/*
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* Enable write base caching so we can do execute in place (XIP)
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* on the flash ROM.
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*/
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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movl $0x0000000f, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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/* Set the default memory type and enable fixed and variable MTRRs. */
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/* TODO: Or also enable fixed MTRRs? Bug in the code? */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %edx, %edx
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movl $(MTRR_DEF_TYPE_EN), %eax
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wrmsr
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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/* Read the range with lodsl. */
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cld
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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movl $CacheBase, %esi
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movl %esi, %edi
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movl $(CacheSize >> 2), %ecx
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/* Zero out the cache-as-ram area. */
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xorl %eax, %eax
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rep stosl
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/*
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* The key point of this CAR code is C7 cache does not turn into
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* "no fill" mode, which is not compatible with general CAR code.
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*/
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movl $(CacheBase + CacheSize - 4), %eax
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movl %eax, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* We need to set EBP? No need. */
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movl %esp, %ebp
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pushl %eax /* BIST */
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call main
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/*
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* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
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* get STACK up, we restore that. It is only needed if we
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* want to go back.
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*/
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/* We don't need CAR from now on. */
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Set the default memory type and enable variable MTRRs. */
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/* TODO: Or also enable fixed MTRRs? Bug in the code? */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %edx, %edx
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movl $(MTRR_DEF_TYPE_EN), %eax
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wrmsr
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/* Enable caching for 0..CACHE_TMP_RAMTOP. */
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movl $MTRR_PHYS_BASE(0), %ecx
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xorl %edx, %edx
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movl $(0x0 | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $MTRR_PHYS_MASK(0), %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff */
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movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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/* Cache XIP_ROM area to speedup coreboot code. */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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xorl %edx, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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invd
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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movl $CONFIG_RAMTOP, %esp
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movl %esp, %ebp
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call copy_and_run
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.Lhlt:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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@ -1,42 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config CPU_VIA_NANO
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bool
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if CPU_VIA_NANO
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select UNKNOWN_TSC_RATE
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select MMX
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CAR_GLOBAL_MIGRATION
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config DCACHE_RAM_BASE
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hex
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default 0xffe00000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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endif # CPU_VIA_NANO
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@ -1,26 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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ramstage-y += nano_init.c
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ramstage-y += update_ucode.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
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cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
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@ -1,4 +0,0 @@
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unsigned int array[3588] =
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{
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#include "../../../../3rdparty/blobs/cpu/via/nano/microcode.h"
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};
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@ -1,196 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "update_ucode.h"
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#include <console/console.h>
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#include <device/device.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#include <delay.h>
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#define MODEL_NANO 0x2
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#define MODEL_NANO_3000_B0 0x8
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#define MODEL_NANO_3000_B2 0xa
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#define NANO_MYSTERIOUS_MSR 0x120e
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static void nano_finish_fid_vid_transition(void)
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{
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msr_t msr;
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/* Wait until the power transition ends */
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int cnt = 0;
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do {
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udelay(16);
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msr = rdmsr(IA32_PERF_STATUS);
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cnt++;
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if (cnt > 128) {
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printk(BIOS_WARNING,
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"Error while updating multiplier and voltage\n");
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break;
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}
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} while (msr.lo & ((1 << 16) | (1 << 17)));
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/* Print the new FID and Voltage */
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u8 cur_vid = (msr.lo >> 0) & 0xff;
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u8 cur_fid = (msr.lo >> 8) & 0xff;
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printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid);
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printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid);
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}
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static void nano_set_max_fid_vid(void)
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{
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msr_t msr;
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/* Get voltage and frequency info */
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msr = rdmsr(IA32_PERF_STATUS);
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u8 min_fid = (msr.hi >> 24);
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u8 max_fid = (msr.hi >> 8) & 0xff;
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u8 min_vid = (msr.hi >> 16) & 0xff;
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u8 max_vid = (msr.hi >> 0) & 0xff;
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u8 cur_vid = (msr.lo >> 0) & 0xff;
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u8 cur_fid = (msr.lo >> 8) & 0xff;
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printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
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cur_fid, min_fid, max_fid);
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printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
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cur_vid, min_vid, max_vid);
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if ((cur_fid != max_fid) || (cur_vid != max_vid)) {
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/* Set highest frequency and VID */
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msr.lo = msr.hi;
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msr.hi = 0;
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wrmsr(IA32_PERF_CTL, msr);
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/* Wait for the transition to complete, otherwise, the CPU
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* might reset itself repeatedly */
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nano_finish_fid_vid_transition();
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}
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/* As a side note, if we didn't update the microcode by this point, the
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* second PLL will not lock correctly. The clock will still be provided
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* by the first PLL, and execution will continue normally, ___until___
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* the CPU switches PLL. Once that happens we will no longer have a
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* working clock source, and the CPU will hang
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* Moral of the story: update the microcode, or don't change FID
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||||
* This check is handled before calling nano_power() */
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}
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static void nano_power(void)
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{
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msr_t msr;
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/* Enable Powersaver */
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 16);
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wrmsr(IA32_MISC_ENABLE, msr);
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||||
/* Enable 6 bit or 7-bit VRM support
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||||
* This MSR is not documented by VIA docs, other than setting these
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* bits */
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msr = rdmsr(NANO_MYSTERIOUS_MSR);
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msr.lo |= ((1 << 7) | (1 << 4));
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||||
/* FIXME: Do we have a 6-bit or 7-bit VRM?
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* set bit [5] for 7-bit, or don't set it for 6 bit VRM
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||||
* This will probably require a Kconfig option
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||||
* My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */
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msr.lo |= (1 << 5);
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wrmsr(NANO_MYSTERIOUS_MSR, msr);
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||||
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/* Set the maximum frequency and voltage */
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||||
nano_set_max_fid_vid();
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||||
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||||
/* Enable TM3 */
|
||||
msr = rdmsr(IA32_MISC_ENABLE);
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||||
msr.lo |= ((1 << 3) | (1 << 13));
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||||
wrmsr(IA32_MISC_ENABLE, msr);
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||||
u8 stepping = (cpuid_eax(0x1)) & 0xf;
|
||||
if (stepping >= MODEL_NANO_3000_B0) {
|
||||
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
|
||||
/* Enable C1e, C2e, C3e, and C4e states */
|
||||
msr = rdmsr(IA32_MISC_ENABLE);
|
||||
msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
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||||
msr.hi |= (1 << 0); /* C4e */
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||||
wrmsr(IA32_MISC_ENABLE, msr);
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||||
}
|
||||
|
||||
/* Lock on Powersaver */
|
||||
msr = rdmsr(IA32_MISC_ENABLE);
|
||||
msr.lo |= (1 << 20);
|
||||
wrmsr(IA32_MISC_ENABLE, msr);
|
||||
}
|
||||
|
||||
static void nano_init(struct device *dev)
|
||||
{
|
||||
struct cpuinfo_x86 c;
|
||||
|
||||
get_fms(&c, dev->device);
|
||||
|
||||
/* We didn't test this on the Nano 1000/2000 series, so warn the user */
|
||||
if (c.x86_mask < MODEL_NANO_3000_B0) {
|
||||
printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
|
||||
"Please report any issues encountered.\n");
|
||||
}
|
||||
switch (c.x86_mask) {
|
||||
case MODEL_NANO:
|
||||
printk(BIOS_INFO, "VIA Nano");
|
||||
break;
|
||||
case MODEL_NANO_3000_B0:
|
||||
printk(BIOS_INFO, "VIA Nano 3000 rev B0");
|
||||
break;
|
||||
case MODEL_NANO_3000_B2:
|
||||
printk(BIOS_INFO, "VIA Nano 3000 rev B2");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask);
|
||||
}
|
||||
printk(BIOS_INFO, "\n");
|
||||
|
||||
/* We only read microcode from CBFS. If we don't have any microcode in
|
||||
* CBFS, we'll just get back with 0 updates. User choice FTW. */
|
||||
unsigned int n_updates = nano_update_ucode();
|
||||
|
||||
if (n_updates != 0){
|
||||
nano_power();
|
||||
} else {
|
||||
/* Changing the frequency or voltage without first updating the
|
||||
* microcode will hang the CPU, so just don't do it */
|
||||
printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n"
|
||||
" Will not change frequency, as this may hang the CPU.\n");
|
||||
}
|
||||
|
||||
/* Turn on cache */
|
||||
x86_enable_cache();
|
||||
/* Set up Memory Type Range Registers */
|
||||
x86_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
/* Enable the local CPU APICs */
|
||||
setup_lapic();
|
||||
}
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = nano_init,
|
||||
};
|
||||
|
||||
static const struct cpu_device_id cpu_table[] = {
|
||||
{X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series
|
||||
{X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0
|
||||
{X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct cpu_driver driver __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
|
@ -1,143 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "update_ucode.h"
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <console/console.h>
|
||||
#include <stddef.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
|
||||
{
|
||||
printk(BIOS_SPEW, "Attempting to apply microcode update\n");
|
||||
|
||||
msr_t msr;
|
||||
/* Address of ucode block goes in msr.lo for 32-bit mode
|
||||
* Now remember, we need to pass the address of the actual microcode,
|
||||
* not the header. The header is just there to help us. */
|
||||
msr.lo = (unsigned int)(&(ucode->ucode_start));
|
||||
msr.hi = 0;
|
||||
wrmsr(IA32_BIOS_UPDT_TRIG, msr);
|
||||
|
||||
/* Let's see if we updated successfully */
|
||||
msr = rdmsr(MSR_UCODE_UPDATE_STATUS);
|
||||
|
||||
return msr.lo & 0x07;
|
||||
}
|
||||
|
||||
static void nano_print_ucode_info(const nano_ucode_header *ucode)
|
||||
{
|
||||
printk(BIOS_SPEW, "Microcode update information:\n");
|
||||
printk(BIOS_SPEW, "Name: %8s\n", ucode->name);
|
||||
printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
|
||||
ucode->day, ucode->year);
|
||||
}
|
||||
|
||||
static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
|
||||
{
|
||||
/* We must have a valid signature */
|
||||
if (ucode->signature != NANO_UCODE_SIGNATURE)
|
||||
return NANO_UCODE_SIGNATURE_ERROR;
|
||||
/* The size of the head must be exactly 12 double words */
|
||||
if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
|
||||
return NANO_UCODE_WRONG_SIZE;
|
||||
|
||||
/* How about a checksum ? Checksum must be 0
|
||||
* Two's complement done over the entire file, including the header */
|
||||
int i;
|
||||
u32 check = 0;
|
||||
u32 *raw = (void *) ucode;
|
||||
for (i = 0; i < ((ucode->total_size) >> 2); i++) {
|
||||
check += raw[i];
|
||||
}
|
||||
if (check != 0)
|
||||
return NANO_UCODE_CHECKSUM_FAIL;
|
||||
/* Made it here huh? Then it looks valid to us.
|
||||
* If there's anything else wrong, the CPU will reject the update */
|
||||
return NANO_UCODE_VALID;
|
||||
}
|
||||
|
||||
static void nano_print_ucode_status(ucode_update_status stat)
|
||||
{
|
||||
switch (stat)
|
||||
{
|
||||
case UCODE_UPDATE_SUCCESS:
|
||||
printk(BIOS_INFO, "Microcode update successful.\n");
|
||||
break;
|
||||
case UCODE_UPDATE_FAIL:
|
||||
printk(BIOS_ALERT, "Microcode update failed, bad environment."
|
||||
"Update was not applied.\n");
|
||||
break;
|
||||
case UCODE_UPDATE_WRONG_CPU:
|
||||
printk(BIOS_ALERT, "Update not applicable to this CPU.\n");
|
||||
break;
|
||||
case UCODE_INVALID_UPDATE_BLOCK:
|
||||
printk(BIOS_ALERT, "Microcode block invalid."
|
||||
"Update was not applied.\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ALERT, "Unknown status. No update applied.\n");
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int nano_update_ucode(void)
|
||||
{
|
||||
size_t i;
|
||||
unsigned int n_updates = 0;
|
||||
u32 fms = cpuid_eax(0x1);
|
||||
/* Considering we are running with eXecute-In-Place (XIP), there's no
|
||||
* need to worry that accessing data from ROM will slow us down.
|
||||
* Microcode data should be aligned to a 4-byte boundary, but CBFS
|
||||
* already does that for us (Do you, CBFS?) */
|
||||
u32 *ucode_data;
|
||||
size_t ucode_len;
|
||||
|
||||
ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
|
||||
CBFS_TYPE_MICROCODE, &ucode_len);
|
||||
/* Oops, did you forget to include the microcode ? */
|
||||
if (ucode_data == NULL) {
|
||||
printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. "
|
||||
"Aborting microcode updates\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We might do a lot of loops searching for the microcode updates, but
|
||||
* keep in mind, nano_ucode_is_valid searches for the signature before
|
||||
* doing anything else. */
|
||||
for (i = 0; i < (ucode_len >> 2); /* don't increment i here */)
|
||||
{
|
||||
ucode_update_status stat;
|
||||
const nano_ucode_header * ucode = (void *)(&ucode_data[i]);
|
||||
if (nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) {
|
||||
i++;
|
||||
continue;
|
||||
}
|
||||
/* Since we have a valid microcode, there's no need to search
|
||||
* in this region, so we restart our search at the end of this
|
||||
* microcode */
|
||||
i += (ucode->total_size >> 2);
|
||||
/* Is the microcode compatible with our CPU? */
|
||||
if (ucode->applicable_fms != fms) continue;
|
||||
/* For our most curious users */
|
||||
nano_print_ucode_info(ucode);
|
||||
/* The meat of the pie */
|
||||
stat = nano_apply_ucode(ucode);
|
||||
/* The user might want to know how the update went */
|
||||
nano_print_ucode_status(stat);
|
||||
if (stat == UCODE_UPDATE_SUCCESS) n_updates++;
|
||||
}
|
||||
|
||||
return n_updates;
|
||||
}
|
|
@ -1,65 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __UPDATE_UCODE_H
|
||||
#define __UPDATE_UCODE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define MSR_UCODE_UPDATE_STATUS 0x00001205
|
||||
|
||||
#define NANO_UCODE_SIGNATURE 0x53415252
|
||||
#define NANO_UCODE_HEADER_SIZE 0x30
|
||||
|
||||
/* These are values returned by the CPU after we attempt microcode updates.
|
||||
* We care what these values are exactly, so we define them to be sure */
|
||||
typedef enum {
|
||||
UCODE_UPDATE_NOT_ATTEMPTED = 0x0,
|
||||
UCODE_UPDATE_SUCCESS = 0x1,
|
||||
UCODE_UPDATE_FAIL = 0x2,
|
||||
UCODE_UPDATE_WRONG_CPU = 0x3,
|
||||
UCODE_INVALID_UPDATE_BLOCK = 0x4,
|
||||
} ucode_update_status;
|
||||
|
||||
|
||||
typedef enum {
|
||||
NANO_UCODE_VALID = 0, /* We only care that valid == 0 */
|
||||
NANO_UCODE_SIGNATURE_ERROR,
|
||||
NANO_UCODE_WRONG_SIZE,
|
||||
NANO_UCODE_CHECKSUM_FAIL,
|
||||
} ucode_validity;
|
||||
|
||||
typedef struct {
|
||||
u32 signature; /* NANO_UCODE_SIGNATURE */
|
||||
u32 update_revision; /* Revision of the update header */
|
||||
u16 year; /* Year of patch release */
|
||||
u8 day; /* Day of patch release */
|
||||
u8 month; /* Month of patch release */
|
||||
u32 applicable_fms; /* Fam/model/stepping to which ucode applies */
|
||||
u32 checksum; /* Two's complement checksum of ucode+header */
|
||||
u32 loader_revision; /* Revision of hardware ucode update loader*/
|
||||
u32 rfu_1; /* Reserved for future use */
|
||||
u32 payload_size; /* Size of the ucode payload only */
|
||||
u32 total_size; /* Size of the ucode, including header */
|
||||
char name[8]; /* ASCII string of ucode filename */
|
||||
u32 rfu_2; /* Reserved for future use */
|
||||
/* First double-word of the ucode payload
|
||||
* Its address represents the beginning of the ucode update we need to
|
||||
* send to the CPU */
|
||||
u32 ucode_start;
|
||||
|
||||
} nano_ucode_header;
|
||||
|
||||
unsigned int nano_update_ucode(void);
|
||||
|
||||
#endif /* __UPDATE_UCODE_H */
|
Loading…
Reference in New Issue