diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 4e5f37802b..c91e7c8b60 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -29,20 +29,19 @@
 #include <northbridge/intel/x4x/chip.h>
 #include <northbridge/intel/x4x/x4x.h>
 
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+
 static void mch_domain_read_resources(device_t dev)
 {
-	u8 index;
+	u8 index, reg8;
 	u64 tom, touud;
-	u32 tomk, tseg_sizek, tolud, usable_tomk;
+	u32 tomk, tseg_sizek = 0, tolud;
 	u32 pcie_config_base, pcie_config_size;
 	u32 uma_sizek = 0;
 
 	const u32 top32memk = 4 * (GiB / KiB);
 	index = 3;
 
-	/* 1024KiB TSEG */
-	tseg_sizek = 1024;
-
 	pci_domain_read_resources(dev);
 
 	/* Top of Upper Usable DRAM, including remap */
@@ -63,25 +62,51 @@ static void mch_domain_read_resources(device_t dev)
 	tomk = tolud >> 10;
 
 	/* Graphics memory comes next */
+
 	const u16 ggc = pci_read_config16(dev, D0F0_GGC);
 	printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 
 	/* Graphics memory */
 	const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
 	printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
+	tomk -= gms_sizek;
+	uma_sizek += gms_sizek;
 
 	/* GTT Graphics Stolen Memory Size (GGMS) */
 	const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
 	printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
+	tomk -= gsm_sizek;
+	uma_sizek += gsm_sizek;
 
-	uma_sizek = gms_sizek + gsm_sizek + tseg_sizek;
-	usable_tomk = tomk - uma_sizek;
+	printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
+	reg8 = pci_read_config8(dev, D0F0_ESMRAMC);
+	reg8 >>= 1;
+	reg8 &= 3;
+	switch (reg8) {
+	case 0:
+		tseg_sizek = 1024;
+		break;	/* TSEG = 1M */
+	case 1:
+		tseg_sizek = 2048;
+		break;	/* TSEG = 2M */
+	case 2:
+		tseg_sizek = 8192;
+		break;	/* TSEG = 8M */
+	}
+	uma_sizek += tseg_sizek;
+	tomk -= tseg_sizek;
 
-	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
+	printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);
+
+	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
 
 	/* Report the memory regions */
-	ram_resource(dev, index++, 0, 0xa0000 >> 10);
-	ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10)));
+	ram_resource(dev, index++, 0, legacy_hole_base_k);
+	mmio_resource(dev, index++, legacy_hole_base_k,
+			(0xc0000 >> 10) - legacy_hole_base_k);
+	reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+			(0x100000 - 0xc0000) >> 10);
+	ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
 
 	/*
 	 * If >= 4GB installed then memory from TOLUD to 4GB
@@ -95,9 +120,8 @@ static void mch_domain_read_resources(device_t dev)
 	}
 
 	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x "
-			"size=0x%08x\n", usable_tomk << 10, uma_sizek << 10);
-	fixed_mem_resource(dev, index++, usable_tomk, uma_sizek,
-			IORESOURCE_RESERVE);
+		"size=0x%08x\n", tomk << 10, uma_sizek << 10);
+	uma_resource(dev, index++, tomk, uma_sizek);
 
 	/* Reserve high memory where the NB BARs are up to 4GiB */
 	fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,