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mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3 

This change disables unused PCIE RP8 and CLKSRC3.
Without this change sasuke cannot enter into s0ix properly.

BUG=b:176862270
TEST=Built and verified entering s0ix

Change-Id: I0828813ed7924669cb0ff97be2565579762c810f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49300
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Seunghwan Kim 2021-01-11 18:26:36 +09:00 committed by Patrick Georgi
parent 88418a74cf
commit 4c4f916172
1 changed files with 5 additions and 1 deletions
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6
src/mainboard/google/dedede/variants/sasuke/overridetree.cb
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@ -1,4 +1,8 @@
chip soc/intel/jasperlake
# Disable PCIe Root Port 8 (index 7)
register "PcieRpEnable[7]" = "0"
# Disable PCIe Clock Source 4 (index 3)
register "PcieClkSrcUsage[3]" = "0xff"
# USB Port Configuration
register "usb2_ports[0]" = "{
@ -107,7 +111,7 @@ chip soc/intel/jasperlake
end
end # I2C 0
device pci 15.2 on end
device pci 1c.7 on end
device pci 1c.7 off end # PCI Express Root Port 8
device pci 19.0 on
chip drivers/i2c/da7219
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"