From 4c68d8467af294b154281da7a0bbe5c9367e0885 Mon Sep 17 00:00:00 2001
From: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Date: Tue, 1 Aug 2023 11:41:37 +0800
Subject: [PATCH] mb/google/dedede/var/boxy: Add power limits for N4500/N5100

Add PLx from JSL PDG(ID: 613095) in boxy devicetree.

BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
     CPU TDP = 6 Watts, CPU PL4 = 60 Watts

Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 .../google/dedede/variants/boxy/overridetree.cb     | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
index ecf71aeaea..10ae686a8c 100644
--- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
@@ -33,6 +33,19 @@ chip soc/intel/jasperlake
 		},
 	}"
 
+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
 	# Enable Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
 	register "PcieRpEnable[2]" = "1"