Remove extra newlines from the end of all coreboot files.
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
parent
4b48ed8f38
commit
4c72d3612b
1
README
1
README
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@ -102,4 +102,3 @@ were derived from other projects, other (GPL-compatible) licenses may apply.
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Please check the individual source files for details.
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This makes the resulting coreboot images licensed under the GPL, version 2.
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@ -8,4 +8,3 @@ config PAYLOAD_UBOOT
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See http://coreboot.org/Payloads and U-Boot's documentation
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at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
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for more information.
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@ -959,4 +959,3 @@ struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd)
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return ctrl;
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}
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@ -1721,4 +1721,3 @@ static void ast_init_dram_2300(struct drm_device *dev)
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if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT)
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dev_err(dev->pdev, "Timeout while waiting for register\n");
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}
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@ -168,4 +168,3 @@ __main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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call after_cache_as_ram
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@ -175,4 +175,3 @@ typedef struct {
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#define VBT_SIGNATURE 0x54425624
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#endif /* _GMA_H_ */
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@ -158,4 +158,3 @@ void *setup_stack_and_mtrrs(void)
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slot = stack_push32(slot, max_mtrrs);
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return slot;
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}
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@ -39,4 +39,3 @@ config HYBRID_GRAPHICS_GPIO_NUM
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help
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Set a default GPIO that sets the panel LVDS signal routing to
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integrated or discrete GPU.
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@ -136,4 +136,3 @@ endif # SPI_FLASH
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config HAVE_SPI_CONSOLE_SUPPORT
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def_bool n
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@ -64,4 +64,3 @@ void spiconsole_tx_byte(unsigned char c) {
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return;
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}
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@ -33,4 +33,3 @@
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uint16_t wifi_regulatory_domain(void);
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#endif /* _WRDD_H_ */
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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -342,4 +342,3 @@ GPIO_CONTROL olivehill_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -343,4 +343,3 @@ GPIO_CONTROL parmer_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -343,4 +343,3 @@ GPIO_CONTROL thatcher_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -219,4 +219,3 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
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#include "cpuLateInit.h"
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#include "GnbInterface.h"
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#include "PlatformInstall.h"
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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -293,4 +293,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -342,4 +342,3 @@ GPIO_CONTROL imba180_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -345,4 +345,3 @@ GPIO_CONTROL f2a85_m_gpio[] = {
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/* Moving this include up will break AGESA. */
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#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
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@ -345,4 +345,3 @@ GPIO_CONTROL f2a85_m_gpio[] = {
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/* Moving this include up will break AGESA. */
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#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
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@ -343,4 +343,3 @@ GPIO_CONTROL gizmo2_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -342,4 +342,3 @@ GPIO_CONTROL imba180_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -22,4 +22,3 @@ void *cbmem_top(void)
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void *ptr = (void *) ((1ULL << 32) - 1048576);
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return ptr;
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}
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@ -296,4 +296,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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// Instantiate all solution relevant data.
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#include "PlatformInstall.h"
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@ -343,4 +343,3 @@ GPIO_CONTROL gizmo2_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
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{
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// TODO (no displays defined yet)
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}
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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
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{
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// TODO (no displays defined yet)
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -28,4 +28,3 @@ uint8_t board_id(void)
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#endif
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return id;
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -42,4 +42,3 @@
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PIRQ_PIC(F, DISABLE), \
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PIRQ_PIC(G, DISABLE), \
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PIRQ_PIC(H, DISABLE)
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@ -81,4 +81,3 @@
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#define DPTF_CPU_PASSIVE 88
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#define DPTF_CPU_CRITICAL 90
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@ -1,3 +1,2 @@
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config BOARD_GOOGLE_FOSTER
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bool "Foster"
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@ -688,4 +688,3 @@ SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
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#@ tRFC [dvfs dram_timing] = 0x000000b4;
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#@ tFC_lpddr4 [dvfs dram_timing hard_coded] = 0x00000104;
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#@ RL [dvfs dram_timing] = 0x00000006;
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -80,4 +80,3 @@ Method(_PRT)
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})
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}
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}
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@ -29,4 +29,3 @@
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#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
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#include "superio/ite/it8772f/acpi/superio.asl"
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@ -337,4 +337,3 @@ Scope (\_TZ)
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}
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}
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}
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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
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{
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// TODO (no displays defined yet)
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -130,5 +130,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -146,4 +146,3 @@ static void mainboard_enable(device_t dev)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
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{
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// TODO (no displays defined yet)
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -30,4 +30,3 @@ ramstage-y += mainboard.c
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ramstage-y += chromeos.c
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ramstage-y += memlayout.ld
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ramstage-y += boardid.c
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@ -1,3 +1,2 @@
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config BOARD_GOOGLE_REEF
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bool "Reef"
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@ -50,4 +50,3 @@ FLASH 16M {
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# Device ext --> 0xf7f000 to 0xfff000
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UNUSED_HOLE@0xfff000 0x1000
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}
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@ -80,4 +80,3 @@ Method(_PRT)
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})
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}
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}
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@ -29,4 +29,3 @@
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#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
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#include "superio/ite/it8772f/acpi/superio.asl"
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@ -337,4 +337,3 @@ Scope (\_TZ)
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}
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}
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}
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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
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{
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// TODO (no displays defined yet)
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -80,4 +80,3 @@ Method(_PRT)
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})
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}
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}
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@ -29,4 +29,3 @@
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#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
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#include "superio/ite/it8772f/acpi/superio.asl"
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@ -445,4 +445,3 @@ Scope (\_TZ)
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}
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}
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}
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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
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{
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// TODO (no displays defined yet)
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -356,4 +356,3 @@ GPIO_CONTROL hp_abm_gpio[] = {
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#define DFLT_VRM_SLEW_RATE (5000)
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#include "PlatformInstall.h"
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@ -389,4 +389,3 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
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/* AGESA nonsense: this header depends on the definitions above */
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#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
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@ -1,3 +1,2 @@
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config BOARD_INTEL_AMENIA
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bool "Amenia"
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@ -34,4 +34,3 @@ FLASH 8M {
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}
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DEVICE_EXTENSION@7M 1M
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}
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@ -1,2 +1 @@
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#Nothing here yet
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -28,4 +28,3 @@ uint8_t board_id(void)
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#endif
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return id;
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}
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@ -131,5 +131,3 @@ enumerations
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checksums
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checksum 392 415 984
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@ -42,4 +42,3 @@
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PIRQ_PIC(F, DISABLE), \
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PIRQ_PIC(G, DISABLE), \
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PIRQ_PIC(H, DISABLE)
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@ -299,4 +299,3 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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/* AGESA nonsense: this header depends on the definitions above */
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/* Instantiate all solution relevant data. */
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#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>
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@ -389,4 +389,3 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
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/* AGESA nonsense: this header depends on the definitions above */
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#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
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@ -102,4 +102,3 @@ If (PICM) {
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// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
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})
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}
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@ -82,4 +82,3 @@ Scope(\_SB)
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// TRAP(43) // TODO
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}
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}
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@ -146,4 +146,3 @@ enumerations
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checksums
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checksum 392 983 984
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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -190,4 +190,3 @@ void mainboard_romstage_entry(unsigned long bist)
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#endif
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printk(BIOS_SPEW, "exit main()\n");
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||||
}
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||||
|
||||
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@ -295,4 +295,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
|
|||
|
||||
// Instantiate all solution relevant data.
|
||||
#include "PlatformInstall.h"
|
||||
|
||||
|
|
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@ -295,4 +295,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
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|||
|
||||
// Instantiate all solution relevant data.
|
||||
#include "PlatformInstall.h"
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||||
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@ -435,4 +435,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
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*/
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|
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#include "MaranelloInstall.h"
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|
||||
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@ -339,4 +339,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] =
|
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*/
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#include "SanMarinoInstall.h"
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@ -435,4 +435,3 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
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*/
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#include "SanMarinoInstall.h"
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|
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@ -130,4 +130,3 @@ Method (_CRS, 0, Serialized)
|
|||
|
||||
Return (MCRS)
|
||||
}
|
||||
|
||||
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|
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@ -137,5 +137,3 @@ static const struct pci_driver pmc __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_APOLLOLAKE_PMC,
|
||||
};
|
||||
|
||||
|
||||
|
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@ -85,4 +85,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
|
|||
"d" (APM_CNT)
|
||||
);
|
||||
}
|
||||
|
||||
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@ -485,4 +485,3 @@ Device (LNKH)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -18,4 +18,3 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0})
|
|||
Name(\_S3, Package(){0x5,0x5,0x0,0x0})
|
||||
Name(\_S4, Package(){0x6,0x6,0x0,0x0})
|
||||
Name(\_S5, Package(){0x7,0x7,0x0,0x0})
|
||||
|
||||
|
|
|
@ -31,4 +31,3 @@ stash_timestamp:
|
|||
|
||||
/* Restore the BIST value to %eax */
|
||||
movl %ebp, %eax
|
||||
|
||||
|
|
|
@ -34,4 +34,3 @@ unsigned long southcluster_write_acpi_tables(device_t device,
|
|||
unsigned long current, struct acpi_rsdp *rsdp);
|
||||
|
||||
#endif /* _SOC_ACPI_H_ */
|
||||
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
romstage-y += early_spi.c
|
||||
romstage-y += pmc.c
|
||||
romstage-y += romstage.c
|
||||
|
||||
|
|
|
@ -39,4 +39,3 @@ Device (WIFI)
|
|||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
|
@ -174,4 +174,3 @@ typedef struct {
|
|||
} __attribute__((packed)) optionrom_vbt_t;
|
||||
|
||||
#endif /* _COMMON_GMA_H_ */
|
||||
|
||||
|
|
|
@ -23,4 +23,3 @@
|
|||
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
|
||||
|
||||
#endif /* _SOC_ACPI_H_ */
|
||||
|
||||
|
|
|
@ -235,4 +235,3 @@ Device (SBUS)
|
|||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -32,4 +32,3 @@ stash_timestamp:
|
|||
|
||||
/* Restore the BIST value to %eax */
|
||||
movl %ebp, %eax
|
||||
|
||||
|
|
|
@ -34,4 +34,3 @@ unsigned long southcluster_write_acpi_tables(device_t device,
|
|||
unsigned long current, struct acpi_rsdp *rsdp);
|
||||
|
||||
#endif /* _SOC_ACPI_H_ */
|
||||
|
||||
|
|
|
@ -53,4 +53,3 @@ typedef enum {
|
|||
} PCH_SERIAL_IO_CONTROLLER;
|
||||
|
||||
#endif
|
||||
|
||||
|
|
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Reference in New Issue