Remove extra newlines from the end of all coreboot files.

This removes the newlines from all files found by the new
int-015-final-newlines script.

Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Martin Roth 2016-07-28 16:50:48 -06:00
parent 4b48ed8f38
commit 4c72d3612b
116 changed files with 0 additions and 130 deletions

1
README
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@ -102,4 +102,3 @@ were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2. This makes the resulting coreboot images licensed under the GPL, version 2.

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@ -8,4 +8,3 @@ config PAYLOAD_UBOOT
See http://coreboot.org/Payloads and U-Boot's documentation See http://coreboot.org/Payloads and U-Boot's documentation
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
for more information. for more information.

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@ -959,4 +959,3 @@ struct usbdev_ctrl *dwc2_udc_init(device_descriptor_t *dd)
return ctrl; return ctrl;
} }

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@ -1721,4 +1721,3 @@ static void ast_init_dram_2300(struct drm_device *dev)
if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT) if (timeout >= COREBOOT_AST_FAILOVER_TIMEOUT)
dev_err(dev->pdev, "Timeout while waiting for register\n"); dev_err(dev->pdev, "Timeout while waiting for register\n");
} }

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@ -168,4 +168,3 @@ __main:
post_code(POST_PREPARE_RAMSTAGE) post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */ cld /* Clear direction flag. */
call after_cache_as_ram call after_cache_as_ram

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@ -175,4 +175,3 @@ typedef struct {
#define VBT_SIGNATURE 0x54425624 #define VBT_SIGNATURE 0x54425624
#endif /* _GMA_H_ */ #endif /* _GMA_H_ */

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@ -158,4 +158,3 @@ void *setup_stack_and_mtrrs(void)
slot = stack_push32(slot, max_mtrrs); slot = stack_push32(slot, max_mtrrs);
return slot; return slot;
} }

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@ -39,4 +39,3 @@ config HYBRID_GRAPHICS_GPIO_NUM
help help
Set a default GPIO that sets the panel LVDS signal routing to Set a default GPIO that sets the panel LVDS signal routing to
integrated or discrete GPU. integrated or discrete GPU.

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@ -136,4 +136,3 @@ endif # SPI_FLASH
config HAVE_SPI_CONSOLE_SUPPORT config HAVE_SPI_CONSOLE_SUPPORT
def_bool n def_bool n

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@ -64,4 +64,3 @@ void spiconsole_tx_byte(unsigned char c) {
return; return;
} }

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@ -33,4 +33,3 @@
uint16_t wifi_regulatory_domain(void); uint16_t wifi_regulatory_domain(void);
#endif /* _WRDD_H_ */ #endif /* _WRDD_H_ */

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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -342,4 +342,3 @@ GPIO_CONTROL olivehill_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -343,4 +343,3 @@ GPIO_CONTROL parmer_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -343,4 +343,3 @@ GPIO_CONTROL thatcher_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -219,4 +219,3 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -293,4 +293,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -342,4 +342,3 @@ GPIO_CONTROL imba180_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -345,4 +345,3 @@ GPIO_CONTROL f2a85_m_gpio[] = {
/* Moving this include up will break AGESA. */ /* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>

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@ -345,4 +345,3 @@ GPIO_CONTROL f2a85_m_gpio[] = {
/* Moving this include up will break AGESA. */ /* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>

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@ -343,4 +343,3 @@ GPIO_CONTROL gizmo2_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -342,4 +342,3 @@ GPIO_CONTROL imba180_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -22,4 +22,3 @@ void *cbmem_top(void)
void *ptr = (void *) ((1ULL << 32) - 1048576); void *ptr = (void *) ((1ULL << 32) - 1048576);
return ptr; return ptr;
} }

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@ -296,4 +296,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -343,4 +343,3 @@ GPIO_CONTROL gizmo2_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
{ {
// TODO (no displays defined yet) // TODO (no displays defined yet)
} }

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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
{ {
// TODO (no displays defined yet) // TODO (no displays defined yet)
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -28,4 +28,3 @@ uint8_t board_id(void)
#endif #endif
return id; return id;
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -42,4 +42,3 @@
PIRQ_PIC(F, DISABLE), \ PIRQ_PIC(F, DISABLE), \
PIRQ_PIC(G, DISABLE), \ PIRQ_PIC(G, DISABLE), \
PIRQ_PIC(H, DISABLE) PIRQ_PIC(H, DISABLE)

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@ -81,4 +81,3 @@
#define DPTF_CPU_PASSIVE 88 #define DPTF_CPU_PASSIVE 88
#define DPTF_CPU_CRITICAL 90 #define DPTF_CPU_CRITICAL 90

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@ -1,3 +1,2 @@
config BOARD_GOOGLE_FOSTER config BOARD_GOOGLE_FOSTER
bool "Foster" bool "Foster"

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@ -688,4 +688,3 @@ SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
#@ tRFC [dvfs dram_timing] = 0x000000b4; #@ tRFC [dvfs dram_timing] = 0x000000b4;
#@ tFC_lpddr4 [dvfs dram_timing hard_coded] = 0x00000104; #@ tFC_lpddr4 [dvfs dram_timing hard_coded] = 0x00000104;
#@ RL [dvfs dram_timing] = 0x00000006; #@ RL [dvfs dram_timing] = 0x00000006;

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -80,4 +80,3 @@ Method(_PRT)
}) })
} }
} }

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@ -29,4 +29,3 @@
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/ite/it8772f/acpi/superio.asl" #include "superio/ite/it8772f/acpi/superio.asl"

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@ -337,4 +337,3 @@ Scope (\_TZ)
} }
} }
} }

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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
{ {
// TODO (no displays defined yet) // TODO (no displays defined yet)
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };

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@ -130,5 +130,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -146,4 +146,3 @@ static void mainboard_enable(device_t dev)
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
{ {
// TODO (no displays defined yet) // TODO (no displays defined yet)
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -30,4 +30,3 @@ ramstage-y += mainboard.c
ramstage-y += chromeos.c ramstage-y += chromeos.c
ramstage-y += memlayout.ld ramstage-y += memlayout.ld
ramstage-y += boardid.c ramstage-y += boardid.c

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@ -1,3 +1,2 @@
config BOARD_GOOGLE_REEF config BOARD_GOOGLE_REEF
bool "Reef" bool "Reef"

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@ -50,4 +50,3 @@ FLASH 16M {
# Device ext --> 0xf7f000 to 0xfff000 # Device ext --> 0xf7f000 to 0xfff000
UNUSED_HOLE@0xfff000 0x1000 UNUSED_HOLE@0xfff000 0x1000
} }

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@ -80,4 +80,3 @@ Method(_PRT)
}) })
} }
} }

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@ -29,4 +29,3 @@
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/ite/it8772f/acpi/superio.asl" #include "superio/ite/it8772f/acpi/superio.asl"

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@ -337,4 +337,3 @@ Scope (\_TZ)
} }
} }
} }

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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
{ {
// TODO (no displays defined yet) // TODO (no displays defined yet)
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };

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@ -80,4 +80,3 @@ Method(_PRT)
}) })
} }
} }

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@ -29,4 +29,3 @@
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/ite/it8772f/acpi/superio.asl" #include "superio/ite/it8772f/acpi/superio.asl"

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@ -445,4 +445,3 @@ Scope (\_TZ)
} }
} }
} }

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@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
{ {
// TODO (no displays defined yet) // TODO (no displays defined yet)
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };

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@ -356,4 +356,3 @@ GPIO_CONTROL hp_abm_gpio[] = {
#define DFLT_VRM_SLEW_RATE (5000) #define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -389,4 +389,3 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
/* AGESA nonsense: this header depends on the definitions above */ /* AGESA nonsense: this header depends on the definitions above */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>

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@ -1,3 +1,2 @@
config BOARD_INTEL_AMENIA config BOARD_INTEL_AMENIA
bool "Amenia" bool "Amenia"

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@ -34,4 +34,3 @@ FLASH 8M {
} }
DEVICE_EXTENSION@7M 1M DEVICE_EXTENSION@7M 1M
} }

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@ -1,2 +1 @@
#Nothing here yet #Nothing here yet

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -28,4 +28,3 @@ uint8_t board_id(void)
#endif #endif
return id; return id;
} }

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@ -131,5 +131,3 @@ enumerations
checksums checksums
checksum 392 415 984 checksum 392 415 984

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@ -42,4 +42,3 @@
PIRQ_PIC(F, DISABLE), \ PIRQ_PIC(F, DISABLE), \
PIRQ_PIC(G, DISABLE), \ PIRQ_PIC(G, DISABLE), \
PIRQ_PIC(H, DISABLE) PIRQ_PIC(H, DISABLE)

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@ -299,4 +299,3 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
/* AGESA nonsense: this header depends on the definitions above */ /* AGESA nonsense: this header depends on the definitions above */
/* Instantiate all solution relevant data. */ /* Instantiate all solution relevant data. */
#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>

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@ -389,4 +389,3 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
/* AGESA nonsense: this header depends on the definitions above */ /* AGESA nonsense: this header depends on the definitions above */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>

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@ -102,4 +102,3 @@ If (PICM) {
// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
}) })
} }

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@ -82,4 +82,3 @@ Scope(\_SB)
// TRAP(43) // TODO // TRAP(43) // TODO
} }
} }

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@ -146,4 +146,3 @@ enumerations
checksums checksums
checksum 392 983 984 checksum 392 983 984

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@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };

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@ -190,4 +190,3 @@ void mainboard_romstage_entry(unsigned long bist)
#endif #endif
printk(BIOS_SPEW, "exit main()\n"); printk(BIOS_SPEW, "exit main()\n");
} }

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@ -295,4 +295,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -295,4 +295,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data. // Instantiate all solution relevant data.
#include "PlatformInstall.h" #include "PlatformInstall.h"

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@ -435,4 +435,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
*/ */
#include "MaranelloInstall.h" #include "MaranelloInstall.h"

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@ -339,4 +339,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] =
*/ */
#include "SanMarinoInstall.h" #include "SanMarinoInstall.h"

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@ -435,4 +435,3 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
*/ */
#include "SanMarinoInstall.h" #include "SanMarinoInstall.h"

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@ -130,4 +130,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS) Return (MCRS)
} }

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@ -137,5 +137,3 @@ static const struct pci_driver pmc __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL, .vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_APOLLOLAKE_PMC, .device = PCI_DEVICE_ID_APOLLOLAKE_PMC,
}; };

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@ -85,4 +85,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
"d" (APM_CNT) "d" (APM_CNT)
); );
} }

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@ -485,4 +485,3 @@ Device (LNKH)
} }
} }
} }

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@ -18,4 +18,3 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0})
Name(\_S3, Package(){0x5,0x5,0x0,0x0}) Name(\_S3, Package(){0x5,0x5,0x0,0x0})
Name(\_S4, Package(){0x6,0x6,0x0,0x0}) Name(\_S4, Package(){0x6,0x6,0x0,0x0})
Name(\_S5, Package(){0x7,0x7,0x0,0x0}) Name(\_S5, Package(){0x7,0x7,0x0,0x0})

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@ -31,4 +31,3 @@ stash_timestamp:
/* Restore the BIST value to %eax */ /* Restore the BIST value to %eax */
movl %ebp, %eax movl %ebp, %eax

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@ -34,4 +34,3 @@ unsigned long southcluster_write_acpi_tables(device_t device,
unsigned long current, struct acpi_rsdp *rsdp); unsigned long current, struct acpi_rsdp *rsdp);
#endif /* _SOC_ACPI_H_ */ #endif /* _SOC_ACPI_H_ */

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@ -1,4 +1,3 @@
romstage-y += early_spi.c romstage-y += early_spi.c
romstage-y += pmc.c romstage-y += pmc.c
romstage-y += romstage.c romstage-y += romstage.c

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@ -39,4 +39,3 @@ Device (WIFI)
} }
} }

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@ -174,4 +174,3 @@ typedef struct {
} __attribute__((packed)) optionrom_vbt_t; } __attribute__((packed)) optionrom_vbt_t;
#endif /* _COMMON_GMA_H_ */ #endif /* _COMMON_GMA_H_ */

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@ -23,4 +23,3 @@
void acpi_fill_in_fadt(acpi_fadt_t *fadt); void acpi_fill_in_fadt(acpi_fadt_t *fadt);
#endif /* _SOC_ACPI_H_ */ #endif /* _SOC_ACPI_H_ */

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@ -235,4 +235,3 @@ Device (SBUS)
} }
#endif #endif
} }

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@ -32,4 +32,3 @@ stash_timestamp:
/* Restore the BIST value to %eax */ /* Restore the BIST value to %eax */
movl %ebp, %eax movl %ebp, %eax

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@ -34,4 +34,3 @@ unsigned long southcluster_write_acpi_tables(device_t device,
unsigned long current, struct acpi_rsdp *rsdp); unsigned long current, struct acpi_rsdp *rsdp);
#endif /* _SOC_ACPI_H_ */ #endif /* _SOC_ACPI_H_ */

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@ -53,4 +53,3 @@ typedef enum {
} PCH_SERIAL_IO_CONTROLLER; } PCH_SERIAL_IO_CONTROLLER;
#endif #endif

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