soc/intel/skylake: Clean up Kconfig

This does the following:
- select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1)
- Remove stale Kconfig option on intel/saddlebrook
- select SOC_INTEL_KABYLAKE on intel/kblrvp

Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-06-17 14:30:10 +02:00 committed by Patrick Georgi
parent e07eb5f173
commit 4c7979a241
8 changed files with 9 additions and 14 deletions

View File

@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
select SOC_INTEL_KABYLAKE
select SKYLAKE_SOC_PCH_H
select MAINBOARD_USES_FSP2_0
select GENERIC_SPD_BIN
select SUPERIO_NUVOTON_NCT6791D
select SUPERIO_NUVOTON_NCT6776_COM_A

View File

@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_KABYLAKE
config VBOOT

View File

@ -17,7 +17,6 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
select SOC_INTEL_KABYLAKE
select MAINBOARD_HAS_SPI_TPM_CR50

View File

@ -13,7 +13,6 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
select SOC_INTEL_KABYLAKE
select MAINBOARD_HAS_TPM2

View File

@ -9,9 +9,8 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8
select SOC_INTEL_SKYLAKE
select SOC_INTEL_KABYLAKE
select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11
select MAINBOARD_USES_FSP2_0
select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM

View File

@ -29,14 +29,10 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_SKYLAKE
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776_COM_A
select SADDLEBROOK_USES_FSP1_1
select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION
select USE_INTEL_FSP_MP_INIT
config SADDLEBROOK_USES_FSP1_1
bool "FSP driver 1.1"
config IRQ_SLOT_COUNT
int
default 18

View File

@ -1,16 +1,20 @@
config SOC_INTEL_COMMON_SKYLAKE_BASE
bool
config SOC_INTEL_SKYLAKE
bool
select SOC_INTEL_COMMON_SKYLAKE_BASE
help
Intel Skylake support
config SOC_INTEL_KABYLAKE
bool
default n
select SOC_INTEL_SKYLAKE
select SOC_INTEL_COMMON_SKYLAKE_BASE
select MAINBOARD_USES_FSP2_0
help
Intel Kabylake support
if SOC_INTEL_SKYLAKE
if SOC_INTEL_COMMON_SKYLAKE_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y

View File

@ -1,4 +1,4 @@
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
ifeq ($(CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE),y)
subdirs-y += nhlt
subdirs-y += romstage