From 4c7ef81a23de1e2e9dd620347817e2ccf2f49a37 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 18:04:57 +0200 Subject: [PATCH] sb/intel/lynxpoint: Use common early SPI code Change-Id: I6c6fbed077d2f169736aee77af3783c847cf3a06 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42666 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/lynxpoint/bootblock.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index b015ea28d1..d142d3e6b7 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -2,25 +2,9 @@ #include #include +#include #include "pch.h" -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); -} - - static void map_rcba(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); @@ -60,7 +44,7 @@ static void set_spi_speed(void) void bootblock_early_southbridge_init(void) { map_rcba(); - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); enable_port80_on_lpc(); set_spi_speed();