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Peppy, Haswell: refactor and create set_translation_table function in haswell/gma.c 

The code to set the graphics translation table has been in the
mainboards, but should be in the northbridge support code.

Move the function, give it a better name, and enable support for > 4
GiB while we're at it, in the remote possibility that we get some 8
GiB haswell boards.

Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171160
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit d5a429498147c479eb51477927e146de809effce)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6741
Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich 2013-09-30 15:57:21 -07:00 committed by Isaac Christensen
parent 8414d3c0b4
commit 4c8465cfac
3 changed files with 43 additions and 39 deletions
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42
src/mainboard/google/peppy/gma.c
View File

@ -43,6 +43,7 @@
#include <cpu/x86/msr.h>
#include <edid.h>
#include <drivers/intel/gma/i915.h>
#include <northbridge/intel/haswell/haswell.h>
#include "mainboard.h"
/*
@ -90,45 +91,8 @@ static unsigned int *mmio;
static unsigned int graphics;
static unsigned int physbase;
/* GTT is the Global Translation Table for the graphics pipeline.
* It is used to translate graphics addresses to physical
* memory addresses. As in the CPU, GTTs map 4K pages.
* The setgtt function adds a further bit of flexibility:
* it allows you to set a range (the first two parameters) to point
* to a physical address (third parameter);the physical address is
* incremented by a count (fourth parameter) for each GTT in the
* range.
* Why do it this way? For ultrafast startup,
* we can point all the GTT entries to point to one page,
* and set that page to 0s:
* memset(physbase, 0, 4096);
* setgtt(0, 4250, physbase, 0);
* this takes about 2 ms, and is a win because zeroing
* the page takes a up to 200 ms.
* This call sets the GTT to point to a linear range of pages
* starting at physbase.
*/
#define GTT_PTE_BASE (2 << 20)
int intel_dp_bw_code_to_link_rate(u8 link_bw);
static void
setgtt(int start, int end, unsigned long base, int inc)
{
int i;
for(i = start; i < end; i++){
u32 word = base + i*inc;
/* note: we've confirmed by checking
* the values that mrc does no
* useful setup before we run this.
*/
gtt_write(GTT_PTE_BASE + i * 4, word|1);
gtt_read(GTT_PTE_BASE + i * 4);
}
}
static int i915_init_done = 0;
/* fill the palette. */
@ -378,10 +342,10 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
2. Developer/Recovery mode: Set up a tasteful color
so people know we are alive. */
if (init_fb || show_test) {
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 4096);
memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
} else {
setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 0);
memset((void*)graphics, 0, 4096);
}

39
src/northbridge/intel/haswell/gma.c
View File

@ -127,6 +127,45 @@ u32 map_oprom_vendev(u32 vendev)
return new_vendev;
}
/* GTT is the Global Translation Table for the graphics pipeline.
* It is used to translate graphics addresses to physical
* memory addresses. As in the CPU, GTTs map 4K pages.
* The setgtt function adds a further bit of flexibility:
* it allows you to set a range (the first two parameters) to point
* to a physical address (third parameter);the physical address is
* incremented by a count (fourth parameter) for each GTT in the
* range.
* Why do it this way? For ultrafast startup,
* we can point all the GTT entries to point to one page,
* and set that page to 0s:
* memset(physbase, 0, 4096);
* setgtt(0, 4250, physbase, 0);
* this takes about 2 ms, and is a win because zeroing
* the page takes a up to 200 ms.
* This call sets the GTT to point to a linear range of pages
* starting at physbase.
*/
#define GTT_PTE_BASE (2 << 20)
void
set_translation_table(int start, int end, u64 base, int inc)
{
int i;
for(i = start; i < end; i++){
u64 physical_address = base + i*inc;
/* swizzle the 32:39 bits to 4:11 */
u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1;
/* note: we've confirmed by checking
* the values that mrc does no
* useful setup before we run this.
*/
gtt_write(GTT_PTE_BASE + i * 4, word);
gtt_read(GTT_PTE_BASE + i * 4);
}
}
static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)

1
src/northbridge/intel/haswell/haswell.h
View File

@ -202,6 +202,7 @@ void intel_northbridge_haswell_finalize_smm(void);
#else /* !__SMM__ */
void haswell_early_initialization(int chipset_type);
void haswell_late_initialization(void);
void set_translation_table(int start, int end, u64 base, int inc);
/* debugging functions */
void print_pci_devices(void);