Peppy, Haswell: refactor and create set_translation_table function in haswell/gma.c
The code to set the graphics translation table has been in the mainboards, but should be in the northbridge support code. Move the function, give it a better name, and enable support for > 4 GiB while we're at it, in the remote possibility that we get some 8 GiB haswell boards. Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171160 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit d5a429498147c479eb51477927e146de809effce) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6741 Tested-by: build bot (Jenkins)
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@ -43,6 +43,7 @@
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include "mainboard.h"
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/*
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@ -90,45 +91,8 @@ static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned int physbase;
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/* GTT is the Global Translation Table for the graphics pipeline.
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* It is used to translate graphics addresses to physical
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* memory addresses. As in the CPU, GTTs map 4K pages.
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* The setgtt function adds a further bit of flexibility:
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* it allows you to set a range (the first two parameters) to point
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* to a physical address (third parameter);the physical address is
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* incremented by a count (fourth parameter) for each GTT in the
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* range.
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* Why do it this way? For ultrafast startup,
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* we can point all the GTT entries to point to one page,
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* and set that page to 0s:
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* memset(physbase, 0, 4096);
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* setgtt(0, 4250, physbase, 0);
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* this takes about 2 ms, and is a win because zeroing
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* the page takes a up to 200 ms.
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* This call sets the GTT to point to a linear range of pages
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* starting at physbase.
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*/
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#define GTT_PTE_BASE (2 << 20)
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int intel_dp_bw_code_to_link_rate(u8 link_bw);
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static void
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setgtt(int start, int end, unsigned long base, int inc)
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{
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int i;
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for(i = start; i < end; i++){
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u32 word = base + i*inc;
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/* note: we've confirmed by checking
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* the values that mrc does no
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* useful setup before we run this.
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*/
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gtt_write(GTT_PTE_BASE + i * 4, word|1);
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gtt_read(GTT_PTE_BASE + i * 4);
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}
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}
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static int i915_init_done = 0;
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/* fill the palette. */
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@ -378,10 +342,10 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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2. Developer/Recovery mode: Set up a tasteful color
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so people know we are alive. */
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if (init_fb || show_test) {
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
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set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 4096);
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memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
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} else {
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
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set_translation_table(0, FRAME_BUFFER_PAGES, physbase, 0);
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memset((void*)graphics, 0, 4096);
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}
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@ -127,6 +127,45 @@ u32 map_oprom_vendev(u32 vendev)
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return new_vendev;
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}
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/* GTT is the Global Translation Table for the graphics pipeline.
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* It is used to translate graphics addresses to physical
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* memory addresses. As in the CPU, GTTs map 4K pages.
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* The setgtt function adds a further bit of flexibility:
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* it allows you to set a range (the first two parameters) to point
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* to a physical address (third parameter);the physical address is
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* incremented by a count (fourth parameter) for each GTT in the
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* range.
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* Why do it this way? For ultrafast startup,
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* we can point all the GTT entries to point to one page,
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* and set that page to 0s:
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* memset(physbase, 0, 4096);
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* setgtt(0, 4250, physbase, 0);
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* this takes about 2 ms, and is a win because zeroing
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* the page takes a up to 200 ms.
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* This call sets the GTT to point to a linear range of pages
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* starting at physbase.
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*/
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#define GTT_PTE_BASE (2 << 20)
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void
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set_translation_table(int start, int end, u64 base, int inc)
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{
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int i;
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for(i = start; i < end; i++){
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u64 physical_address = base + i*inc;
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/* swizzle the 32:39 bits to 4:11 */
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u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1;
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/* note: we've confirmed by checking
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* the values that mrc does no
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* useful setup before we run this.
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*/
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gtt_write(GTT_PTE_BASE + i * 4, word);
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gtt_read(GTT_PTE_BASE + i * 4);
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}
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}
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static struct resource *gtt_res = NULL;
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u32 gtt_read(u32 reg)
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@ -202,6 +202,7 @@ void intel_northbridge_haswell_finalize_smm(void);
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#else /* !__SMM__ */
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void haswell_early_initialization(int chipset_type);
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void haswell_late_initialization(void);
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void set_translation_table(int start, int end, u64 base, int inc);
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/* debugging functions */
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void print_pci_devices(void);
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