soc/intel/apollolake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. Change-Id: I5aea15511c52d1191babf551feb237f4144683e4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -30,6 +30,7 @@
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/xdci.h>
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#include <fsp/api.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/cpulib.h>
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@ -585,6 +586,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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glk_fsp_silicon_init_params_cb(cfg, silconfig);
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glk_fsp_silicon_init_params_cb(cfg, silconfig);
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else
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else
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apl_fsp_silicon_init_params_cb(cfg, silconfig);
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apl_fsp_silicon_init_params_cb(cfg, silconfig);
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = dev_find_slot(0, PCH_DEVFN_XDCI);
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if (!xdci_can_enable())
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dev->enabled = 0;
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silconfig->UsbOtg = dev->enabled;
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}
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}
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struct chip_operations soc_intel_apollolake_ops = {
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struct chip_operations soc_intel_apollolake_ops = {
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@ -54,7 +54,7 @@ static void configure_host_mode_port0(struct device *dev)
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* enabled. If it's disabled assume the switch was already done
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* enabled. If it's disabled assume the switch was already done
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* in FSP.
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* in FSP.
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*/
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*/
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if (!dev->enabled || !xdci_dev->enabled)
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if (!dev->enabled || !xdci_dev->enabled || !xdci_can_enable())
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return;
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return;
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printk(BIOS_INFO, "Putting port 0 into host mode.\n");
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printk(BIOS_INFO, "Putting port 0 into host mode.\n");
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