Support for Lanner EM-8510 Board
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> --- src/mainboard/Kconfig | 8 ++ src/mainboard/lanner/Kconfig | 8 ++ src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++ src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++ src/mainboard/lanner/em8510/chip.h | 23 +++++++ src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++ src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++ src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++ src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++ src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++ 10 files changed, 418 insertions(+), 0 deletions(-) create mode 100644 src/mainboard/lanner/Kconfig create mode 100644 src/mainboard/lanner/em8510/Kconfig create mode 100644 src/mainboard/lanner/em8510/Makefile.inc create mode 100644 src/mainboard/lanner/em8510/chip.h create mode 100644 src/mainboard/lanner/em8510/cmos.layout create mode 100644 src/mainboard/lanner/em8510/devicetree.cb create mode 100644 src/mainboard/lanner/em8510/irq_tables.c create mode 100644 src/mainboard/lanner/em8510/mainboard.c create mode 100644 src/mainboard/lanner/em8510/romstage.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Andreas Schultz
Stefan Reinauer
parent
b6b29dbbb9
commit
4c94c05b7c
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@ -64,6 +64,8 @@ config VENDOR_JETWAY
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bool "Jetway"
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config VENDOR_KONTRON
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bool "Kontron"
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config VENDOR_LANNER
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bool "Lanner"
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config VENDOR_LIPPERT
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bool "Lippert"
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config VENDOR_MITAC
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@ -268,6 +270,11 @@ config MAINBOARD_VENDOR
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default "Kontron"
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depends on VENDOR_KONTRON
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config MAINBOARD_VENDOR
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string
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default "Lanner"
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depends on VENDOR_LANNER
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config MAINBOARD_VENDOR
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string
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default "Lippert"
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@ -443,6 +450,7 @@ source "src/mainboard/intel/Kconfig"
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source "src/mainboard/iwill/Kconfig"
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source "src/mainboard/jetway/Kconfig"
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source "src/mainboard/kontron/Kconfig"
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source "src/mainboard/lanner/Kconfig"
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source "src/mainboard/lippert/Kconfig"
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source "src/mainboard/mitac/Kconfig"
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source "src/mainboard/msi/Kconfig"
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@ -0,0 +1,8 @@
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choice
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prompt "Mainboard model"
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depends on VENDOR_LANNER
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source "src/mainboard/lanner/em8510/Kconfig"
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endchoice
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@ -0,0 +1,38 @@
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config BOARD_LANNER_EM8510
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bool "EM-8510"
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select ARCH_X86
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select CPU_INTEL_SOCKET_MPGA479M
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select NORTHBRIDGE_INTEL_I855
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select SOUTHBRIDGE_INTEL_I82801DX
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select SUPERIO_WINBOND_W83627THF
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_HARD_RESET
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select BOARD_ROMSIZE_KB_512
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select USE_DCACHE_RAM
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select TINY_BOOTBLOCK
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config MAINBOARD_DIR
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string
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default lanner/em8510
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depends on BOARD_LANNER_EM8510
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config MAINBOARD_PART_NUMBER
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string
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default "EM-8510"
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depends on BOARD_LANNER_EM8510
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config DCACHE_RAM_BASE
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hex
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default 0xffdf8000
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depends on BOARD_LANNER_EM8510
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_LANNER_EM8510
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config IRQ_SLOT_COUNT
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int
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default 10
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depends on BOARD_LANNER_EM8510
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Travelping GmbH <info@travelping.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ROMCCFLAGS := -mcpu=p3 -O
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Travelping GmbH <info@travelping.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,74 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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@ -0,0 +1,60 @@
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chip northbridge/intel/i855
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/intel/i82801dx
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# pci 11.0 on end
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# pci 11.1 on end
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# pci 11.2 on end
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# pci 11.3 on end
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# pci 11.4 on end
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# pci 11.5 on end
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# pci 11.6 on end
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# pci 12.0 on end
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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device pci 1f.0 on
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chip superio/winbond/w83627thf # link 1
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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register "com1" = "{1}"
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# register "com1" = "{1, 0, 0x3f8, 4}"
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# register "lpt" = "{1}"
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end
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end
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end
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end
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device lapic_cluster 0 on
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chip cpu/intel/socket_mPGA479M
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device lapic 0 on end
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end
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end
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end
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@ -0,0 +1,56 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Travelping GmbH <info@travelping.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * 10, /* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x1f << 3) | 0x0, /* Interrupt router dev */
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0x1e20, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x24cc, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x39, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x01, (0x0f << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x1, 0x0},
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{0x01, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x2, 0x0},
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{0x01, (0x05 << 3) | 0x0, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x3, 0x0},
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{0x01, (0x06 << 3) | 0x0, {{0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}, {0x68, 0xdeb8}}, 0x4, 0x0},
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{0x01, (0x07 << 3) | 0x0, {{0x6a, 0xdeb8}, {0x6b, 0xdeb8}, {0x68, 0xdeb8}, {0x69, 0xdeb8}}, 0x5, 0x0},
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{0x01, (0x09 << 3) | 0x0, {{0x6b, 0xdeb8}, {0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}}, 0x6, 0x0},
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{0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x02 << 3) | 0x0, {{0x60, 0xdeb8}, {0x60, 0xdeb8}, {0x60, 0xdeb8}, {0x60, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x1f << 3) | 0x0, {{0x62, 0xdeb8}, {0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x1d << 3) | 0x0, {{0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x6b, 0xdeb8}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Travelping GmbH <info@travelping.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("LANNER EM-8510 Mainboard")
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};
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||||
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||||
|
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@ -0,0 +1,103 @@
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Original take from digitallogic/adl855pc
|
||||
*
|
||||
* Copyright (C) 2010 Travelping GmbH <info@travelping.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <stdlib.h>
|
||||
#include "pc80/udelay_io.c"
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <console/console.h>
|
||||
#include "lib/ramtest.c"
|
||||
#include "southbridge/intel/i82801dx/i82801dx.h"
|
||||
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
|
||||
#include "northbridge/intel/i855/raminit.h"
|
||||
#include "northbridge/intel/i855/debug.c"
|
||||
#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627THF_SP1)
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/i855/raminit.c"
|
||||
#include "northbridge/intel/i855/reset_test.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 1),
|
||||
.channel0 = { (0xa<<3)|0, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
if (bist == 0) {
|
||||
#if 0
|
||||
enable_lapic();
|
||||
init_timer();
|
||||
#endif
|
||||
}
|
||||
|
||||
w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
#endif
|
||||
|
||||
if(!bios_reset_detected()) {
|
||||
enable_smbus();
|
||||
#if 1
|
||||
dump_spd_registers(&memctrl[0]);
|
||||
dump_smbus_registers();
|
||||
#endif
|
||||
|
||||
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
|
||||
|
||||
}
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_device(PCI_DEV(0, 0, 0));
|
||||
|
||||
// Check all of memory
|
||||
ram_check(0x00000000, msr.lo+(msr.hi<<32));
|
||||
// Check 16MB of memory @ 0
|
||||
ram_check(0x00000000, 0x01000000);
|
||||
// Check 16MB of memory @ 2GB
|
||||
ram_check(0x80000000, 0x81000000);
|
||||
#endif
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue