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soc/intel/tigerlake: Configure THC 

Enable/Disable THCx though devicetree

BUG=None
BRANCH=None
TEST=Boot and check FSP log for THC setting

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: If7683969161be67f68f441c28c80503de39079b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-05-20 13:09:39 -07:00 committed by Patrick Georgi
parent c356861239
commit 4cabf789fd
1 changed files with 18 additions and 0 deletions
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18
src/soc/intel/tigerlake/fsp_params.c
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@ -17,6 +17,11 @@
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
#include <string.h> #include <string.h>
/* THC assignment definition */
#define THC_NONE 0
#define THC_0 1
#define THC_1 2
/* /*
* Chip config parameter PcieRpL1Substates uses (UPD value + 1) * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
* because UPD value of 0 for PcieRpL1Substates means disabled for FSP. * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@ -221,6 +226,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
else else
params->VmdEnable = 0; params->VmdEnable = 0;
/* THC */
dev = pcidev_path_on_root(PCH_DEVFN_THC0);
if (!dev)
params->ThcPort0Assignment = 0;
else
params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE;
dev = pcidev_path_on_root(PCH_DEVFN_THC1);
if (!dev)
params->ThcPort1Assignment = 0;
else
params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */ /* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;