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soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP 

The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs
can be "locked" and this patch adds the definition for that.

BUG=b:164489598

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tim Wawrzynczak 2020-09-01 16:10:06 -06:00 committed by Patrick Georgi
parent 62669a24ea
commit 4cba419676
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/common/block/include/intelblocks/msr.h
View File

@ -106,8 +106,9 @@
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
/* MTRR_CAP_MSR bits */
#define SMRR_SUPPORTED (1<<11)
#define PRMRR_SUPPORTED (1<<12)
#define SMRR_SUPPORTED (1<<11)
#define PRMRR_SUPPORTED (1<<12)
#define SMRR_LOCK_SUPPORTED (1<<14)
#define SGX_SUPPORTED (1<<2)
/* Intel SDM: Table 36-6.