YhLu fix on multi ht and s2885
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
2f92e14dd4
commit
4cd79f3f86
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@ -120,10 +120,6 @@ mainboardinit cpu/i386/bist32_fail.inc
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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@ -141,8 +137,7 @@ end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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end
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mainboardinit cpu/k8/enable_mmx_sse.inc
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@ -151,16 +151,13 @@ static void main(void)
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{
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.udev = PCI_DEV(0, 0x18, 0),
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.upos = 0xc0,
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.devreg = 0xe2,
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.mindev = 1,
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},
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.devreg = 0xe0,
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},
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{
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.udev = PCI_DEV(0, 0x18, 0),
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.upos = 0x80,
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.devreg = 0xe6,
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.mindev = 5,
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},
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.devreg = 0xe4,
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},
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};
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int needs_reset;
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@ -252,8 +252,8 @@ static void setup_s2885_resource_map(void)
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration regin i
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*/
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PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207,
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PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007,
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PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06010207,
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PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000007,
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PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
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};
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@ -12,7 +12,7 @@ static unsigned ht_lookup_slave_capability(device_t dev)
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hdr_type &= 0x7f;
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if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
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(hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
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(hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
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pos = PCI_CAPABILITY_LIST;
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}
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if (pos > PCI_CAP_LIST_NEXT) {
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@ -48,7 +48,7 @@ static void ht_collapse_previous_enumeration(unsigned bus)
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if ((id == 0xffffffff) || (id == 0x00000000) ||
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(id == 0x0000ffff) || (id == 0xffff0000)) {
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(id == 0x0000ffff) || (id == 0xffff0000)) {
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continue;
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}
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pos = ht_lookup_slave_capability(dev);
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@ -63,7 +63,6 @@ static void ht_collapse_previous_enumeration(unsigned bus)
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}
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}
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static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
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{
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/* Handle bugs in valid hypertransport frequency reporting */
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@ -90,27 +89,27 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
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return freq_cap;
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}
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#define LINK_OFFS(WIDTH,FREQ,FREQ_CAP) \
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#define LINK_OFFS(WIDTH,FREQ,FREQ_CAP) \
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(((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
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#define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
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#define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF)
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#define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
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#define PCI_HT_HOST_OFFS LINK_OFFS( \
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PCI_HT_CAP_HOST_WIDTH, \
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PCI_HT_CAP_HOST_FREQ, \
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PCI_HT_CAP_HOST_FREQ_CAP)
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#define PCI_HT_HOST_OFFS LINK_OFFS( \
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PCI_HT_CAP_HOST_WIDTH, \
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PCI_HT_CAP_HOST_FREQ, \
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PCI_HT_CAP_HOST_FREQ_CAP)
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#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
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PCI_HT_CAP_SLAVE_WIDTH0, \
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PCI_HT_CAP_SLAVE_FREQ0, \
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PCI_HT_CAP_SLAVE_FREQ_CAP0)
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#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
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PCI_HT_CAP_SLAVE_WIDTH0, \
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PCI_HT_CAP_SLAVE_FREQ0, \
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PCI_HT_CAP_SLAVE_FREQ_CAP0)
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#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
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PCI_HT_CAP_SLAVE_WIDTH1, \
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PCI_HT_CAP_SLAVE_FREQ1, \
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PCI_HT_CAP_SLAVE_FREQ_CAP1)
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#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
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PCI_HT_CAP_SLAVE_WIDTH1, \
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PCI_HT_CAP_SLAVE_FREQ1, \
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PCI_HT_CAP_SLAVE_FREQ_CAP1)
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static int ht_optimize_link(
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device_t dev1, uint8_t pos1, unsigned offs1,
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@ -212,8 +211,8 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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/* If the chain is enumerated quit */
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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break;
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}
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pos = ht_lookup_slave_capability(dev);
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@ -242,111 +241,130 @@ static int ht_setup_chain(device_t udev, unsigned upos)
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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return reset_needed;
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}
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struct ht_chain {
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device_t udev;
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unsigned upos;
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unsigned devreg;
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unsigned mindev;
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};
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device_t udev;
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unsigned upos;
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unsigned devreg;
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};
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static int ht_setup_chainx(device_t udev, unsigned upos, unsigned next_unitid)
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{
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unsigned last_unitid;
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unsigned uoffs;
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int reset_needed=0;
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uoffs = PCI_HT_HOST_OFFS;
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do {
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uint32_t id;
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uint8_t pos;
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unsigned flags, count;
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device_t dev = PCI_DEV(0, 0, 0);
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last_unitid = next_unitid;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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/* If the chain is enumerated quit */
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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break;
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}
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pos = ht_lookup_slave_capability(dev);
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if (!pos) {
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print_err("HT link capability not found\r\n");
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break;
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}
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/* Setup the Hypertransport link */
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reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
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/* Update the Unitid of the current device */
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flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
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flags &= ~0x1f; /* mask out the bse Unit ID */
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flags |= next_unitid & 0x1f;
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pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
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/* Remeber the location of the last device */
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udev = PCI_DEV(0, next_unitid, 0);
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upos = pos;
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uoffs = PCI_HT_SLAVE1_OFFS;
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/* Compute the number of unitids consumed */
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count = (flags >> 5) & 0x1f;
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next_unitid += count;
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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if(reset_needed!=0) next_unitid |= 0xffff0000;
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return next_unitid;
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}
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static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
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{
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/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
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* On most boards this just happens. If a cpu has multiple
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* non Coherent links the appropriate bus registers for the
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* links needs to be programed to point at bus 0.
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*/
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unsigned next_unitid, last_unitid;
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int reset_needed;
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unsigned uoffs;
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unsigned upos;
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device_t udev;
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int i;
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{
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/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
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* On most boards this just happens. If a cpu has multiple
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* non Coherent links the appropriate bus registers for the
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* links needs to be programed to point at bus 0.
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*/
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unsigned next_unitid;
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int reset_needed;
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unsigned upos;
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device_t udev;
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int i;
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/* Make certain the HT bus is not enumerated */
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ht_collapse_previous_enumeration(0);
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/* Make certain the HT bus is not enumerated */
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ht_collapse_previous_enumeration(0);
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reset_needed = 0;
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next_unitid = 1;
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reset_needed = 0;
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next_unitid = 1;
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for(i=0;i<ht_c_num;i++) {
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#if 0
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unsigned tmp;
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tmp = pci_read_config8(PCI_DEV(0,0x18,1),ht_c[i].devreg);
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#endif
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for(i=0;i<ht_c_num;i++) {
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uint32_t reg;
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uint8_t reg8;
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reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg);
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reg |= (0xff<<24) | 7;
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reg &= ~(0xff<<16);
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pci_write_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg, reg);
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pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg, 0);
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#if CONFIG_MAX_CPUS > 1
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pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg, 0);
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pci_write_config32(PCI_DEV(0,0x19,1), ht_c[i].devreg, reg);
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#endif
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#if CONFIG_MAX_CPUS > 2
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pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg, 0);
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pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg, 0);
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pci_write_config32(PCI_DEV(0,0x1a,1), ht_c[i].devreg, reg);
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pci_write_config32(PCI_DEV(0,0x1b,1), ht_c[i].devreg, reg);
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#endif
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uoffs = PCI_HT_HOST_OFFS;
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upos = ht_c[i].upos;
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udev = ht_c[i].udev;
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do {
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uint32_t id;
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uint8_t pos;
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unsigned flags, count;
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device_t dev = PCI_DEV(0, 0, 0);
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last_unitid = next_unitid;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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/* If the chain is enumerated quit */
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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break;
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}
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pos = ht_lookup_slave_capability(dev);
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if (!pos) {
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print_err("HT link capability not found\r\n");
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break;
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}
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/* Setup the Hypertransport link */
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reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
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//Store dev min
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reg8 = next_unitid & 0xff ;
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upos = ht_c[i].upos;
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udev = ht_c[i].udev;
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/* Update the Unitid of the current device */
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flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
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flags &= ~0x1f; /* mask out the bse Unit ID */
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flags |= next_unitid & 0x1f;
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pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
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next_unitid = ht_setup_chainx(udev,upos,next_unitid);
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if((next_unitid & 0xffff0000) == 0xffff0000) {
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reset_needed |= 1;
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next_unitid &=0x0000ffff;
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}
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/* Remeber the location of the last device */
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udev = PCI_DEV(0, next_unitid, 0);
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upos = pos;
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uoffs = PCI_HT_SLAVE1_OFFS;
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/* Compute the number of unitids consumed */
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count = (flags >> 5) & 0x1f;
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next_unitid += count;
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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#if 0
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pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg, tmp);
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//set dev min
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pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+2, reg8);
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#if CONFIG_MAX_CPUS > 1
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pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg, tmp);
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pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+2, reg8);
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#endif
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#if CONFIG_MAX_CPUS > 2
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pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg, tmp);
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pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg, tmp);
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pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+2, reg8);
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pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+2, reg8);
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#endif
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#else
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pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg, ht_c[i].mindev);
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#if CONFIG_MAX_CPUS > 1
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pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg, ht_c[i].mindev);
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//Set dev max
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reg8 = (next_unitid-1) & 0xff ;
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pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+3, reg8);
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#if CONFIG_MAX_CPUS > 1
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pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+3, reg8);
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#endif
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#if CONFIG_MAX_CPUS > 2
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pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg, ht_c[i].mindev);
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pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg, ht_c[i].mindev);
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#endif
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pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+3, reg8);
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pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+3, reg8);
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#endif
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}
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}
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return reset_needed;
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return reset_needed;
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}
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