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mb/prodrive/hermes: Update PCIe slots in devicetree 

* Drop PcieRpSlotImplemented on internal slots
* Add PCIe port 15 that connected to CNVi/M.2 E

Change-Id: Iaa05affa760b447fc1725e674b12366684a63720
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2020-11-05 11:30:16 +01:00 committed by Patrick Rudolph
parent d9d711c7f5
commit 4ce5b63294
1 changed files with 9 additions and 18 deletions
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27
src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
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@ -185,30 +185,21 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCIe root port 5 (PHY 3)
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 on # PCIe root port 6 (PHY 4)
register "PcieRpSlotImplemented[5]" = "1"
end
device pci 1c.6 on # PCIe root port 7 (PHY 2)
register "PcieRpSlotImplemented[6]" = "1"
end
device pci 1c.7 on # PCIe root port 8 (PHY 1)
register "PcieRpSlotImplemented[7]" = "1"
end
device pci 1c.4 on end # PCIe root port 5 (PHY 3)
device pci 1c.5 on end # PCIe root port 6 (PHY 4)
device pci 1c.6 on end # PCIe root port 7 (PHY 2)
device pci 1c.7 on end # PCIe root port 8 (PHY 1)
device pci 1d.0 on # PCIe root port 9 (M2 M)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.5 on # PCIe root port 14 (PHY 0)
register "PcieRpSlotImplemented[13]" = "1"
device pci 1d.5 on end # PCIe root port 14 (PHY 0)
device pci 1d.6 on end # PCIe root port 15 (BMC)
device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi)
# Disabled when CNVi is present
register "PcieRpSlotImplemented[15]" = "1"
end
device pci 1d.6 on # PCIe root port 15 (BMC)
register "PcieRpSlotImplemented[14]" = "1"
end
device pci 1e.0 on end # UART #0
device pci 1e.1 on end # UART #1
device pci 1e.2 off end # GSPI #0