Get rid of the unnecessary indirection by 'struct mem_controller' for the
Intel 810 chipset (and all boards using it). This isn't required for this chipset as there's only one memory controller. This also helps a lot with romcc register usage, you should see the dreaded "too few registers" less often. Build-tested with all three boards using the Intel 810 chipset. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
76c6c95c1e
commit
4cf5ecf39d
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@ -48,17 +48,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
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#include "northbridge/intel/i82810/raminit.c"
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/* #include "northbridge/intel/i82810/debug.c" */
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#include "sdram/generic_sdram.c"
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = {0x50, 0x51},
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}
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};
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if (bist == 0)
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early_mtrr_init();
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@ -67,7 +59,9 @@ static void main(unsigned long bist)
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console_init();
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report_bist_failure(bist);
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enable_smbus();
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/* dump_spd_registers(&memctrl[0]); */
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sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
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/* dump_spd_registers(); */
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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/* ram_check(0, 640 * 1024); */
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}
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@ -52,17 +52,9 @@ void udelay(int usecs)
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#include "northbridge/intel/i82810/raminit.c"
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#include "northbridge/intel/i82810/debug.c"
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#include "sdram/generic_sdram.c"
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = {0x50, 0x51},
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}
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};
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if (bist == 0)
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early_mtrr_init();
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@ -75,14 +67,11 @@ static void main(unsigned long bist)
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/* Halt if there was a built in self test failure. */
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report_bist_failure(bist);
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/* dump_spd_registers(&memctrl[0]); */
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/* dump_spd_registers(); */
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/* sdram_initialize() runs out of registers. */
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/* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */
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sdram_set_registers(memctrl);
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sdram_set_spd_registers(memctrl);
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sdram_enable(0, memctrl);
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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/* Check RAM. */
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/* ram_check(0, 640 * 1024); */
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@ -37,19 +37,11 @@
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#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
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#include "pc80/udelay_io.c"
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#include "northbridge/intel/i82810/raminit.c"
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#include "sdram/generic_sdram.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = {0x50, 0x51},
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}
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};
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if (bist == 0)
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early_mtrr_init();
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@ -66,7 +58,10 @@ static void main(unsigned long bist)
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enable_smbus();
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report_bist_failure(bist);
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/* dump_spd_registers(&memctrl[0]); */
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sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
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/* dump_spd_registers(); */
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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/* ram_check(0, 640 * 1024); */
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}
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@ -1,11 +1,11 @@
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static void dump_spd_registers(const struct mem_controller *ctrl)
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static void dump_spd_registers(void)
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{
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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for(i = 0; i < DIMM_SOCKETS; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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device = DIMM_SPD_BASE + i;
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if (device) {
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int j;
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print_debug("dimm: ");
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@ -62,22 +62,21 @@ SDRAM configuration functions.
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/**
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* Send the specified RAM command to all DIMMs.
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*
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* @param Memory controller
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* @param TODO
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* @param TODO
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*/
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static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
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uint32_t addr_offset, uint32_t row_offset)
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static void do_ram_command(uint32_t command, uint32_t addr_offset,
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uint32_t row_offset)
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{
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uint8_t reg;
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/* TODO: Support for multiple DIMMs. */
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/* Configure the RAM command. */
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reg = pci_read_config8(ctrl->d0, DRAMT);
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reg = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
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reg &= 0x1f; /* Clear bits 7-5. */
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reg |= command << 5;
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pci_write_config8(ctrl->d0, DRAMT, reg);
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pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg);
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/* RAM_COMMAND_NORMAL affects only the memory controller and
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doesn't need to be "sent" to the DIMMs. */
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@ -101,8 +100,7 @@ DIMM-independant configuration functions.
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/*
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* Set DRP - DRAM Row Population Register (Device 0).
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*/
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static void spd_set_dram_size(const struct mem_controller *ctrl,
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uint32_t row_offset)
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static void spd_set_dram_size(uint32_t row_offset)
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{
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/* The variables drp and dimm_size have to be ints since all the
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* SMBus-related functions return ints, and its just easier this way.
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@ -113,12 +111,12 @@ static void spd_set_dram_size(const struct mem_controller *ctrl,
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for (i = 0; i < DIMM_SOCKETS; i++) {
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/* First check if a DIMM is actually present. */
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if (smbus_read_byte(ctrl->channel0[i], 2) == 4) {
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if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
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print_debug("Found DIMM in slot ");
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print_debug_hex8(i);
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print_debug("\r\n");
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dimm_size = smbus_read_byte(ctrl->channel0[i], 31);
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dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
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/* WISHLIST: would be nice to display it as decimal? */
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print_debug("DIMM is 0x");
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@ -181,7 +179,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl,
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/* If the DIMM is dual-sided, the DRP value is +2 */
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/* TODO: Figure out asymetrical configurations. */
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if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) ==
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if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
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0xff) {
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print_debug("DIMM is dual-sided\r\n");
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dimm_size += 2;
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@ -203,13 +201,13 @@ static void spd_set_dram_size(const struct mem_controller *ctrl,
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print_debug_hex8(drp);
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print_debug("\r\n");
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pci_write_config8(ctrl->d0, DRP, drp);
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pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
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}
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static void set_dram_timing(const struct mem_controller *ctrl)
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static void set_dram_timing(void)
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{
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/* TODO, for now using default, hopefully safe values. */
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// pci_write_config8(ctrl->d0, DRAMT, 0x00);
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// pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00);
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}
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/*
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@ -239,9 +237,9 @@ static void set_dram_timing(const struct mem_controller *ctrl)
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* 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided
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* 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided
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*/
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static void set_dram_buffer_strength(const struct mem_controller *ctrl)
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static void set_dram_buffer_strength(void)
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{
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pci_write_config16(ctrl->d0, BUFF_SC, 0x77da);
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pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, 0x77da);
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}
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/*-----------------------------------------------------------------------------
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@ -250,15 +248,13 @@ Public interface.
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/**
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* TODO.
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*
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* @param Memory controller
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*/
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static void sdram_set_registers(const struct mem_controller *ctrl)
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static void sdram_set_registers(void)
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{
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unsigned long val;
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/* TODO */
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pci_write_config8(ctrl->d0, GMCHCFG, 0x60);
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pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60);
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/* PAMR: Programmable Attributes Register
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* Every pair of bits controls an address range:
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@ -275,49 +271,44 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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*/
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/* Ideally, this should be R/W for as many ranges as possible. */
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pci_write_config8(ctrl->d0, PAM, 0xff);
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pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff);
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/* Enabling the VGA Framebuffer currently screws up the rest of the boot.
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* Disable for now */
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/* Enable 1MB framebuffer. */
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//pci_write_config8(ctrl->d0, SMRAM, 0xC0);
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//pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0);
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//val = pci_read_config16(ctrl->d0, MISSC);
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//val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC);
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/* Preserve reserved bits. */
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//val &= 0xff06;
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/* Set graphics cache window to 32MB, no power throttling. */
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//val |= 0x0001;
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//pci_write_config16(ctrl->d0, MISSC, val);
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//pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val);
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//val = pci_read_config8(ctrl->d0, MISSC2);
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//val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
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/* Enable graphics palettes and clock gating (not optional!) */
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//val |= 0x06;
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//pci_write_config8(ctrl->d0, MISSC2, val);
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//pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
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}
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/**
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* TODO.
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*
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* @param Memory controller
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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static void sdram_set_spd_registers(void)
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{
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/* spd_set_dram_size() moved into sdram_enable() to prevent having
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* to pass a variable between here and there.
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*/
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set_dram_buffer_strength(ctrl);
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set_dram_buffer_strength();
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set_dram_timing(ctrl);
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set_dram_timing();
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}
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/**
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* Enable SDRAM.
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*
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* @param Number of controllers
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* @param Memory controller
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*/
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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static void sdram_enable(void)
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{
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int i;
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@ -327,21 +318,21 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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*/
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uint32_t row_offset;
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spd_set_dram_size(ctrl, row_offset);
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spd_set_dram_size(row_offset);
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/* 1. Apply NOP. */
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PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
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do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset);
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do_ram_command(RAM_COMMAND_NOP, 0, row_offset);
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udelay(200);
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/* 2. Precharge all. Wait tRP. */
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PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
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do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0, row_offset);
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do_ram_command(RAM_COMMAND_PRECHARGE, 0, row_offset);
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udelay(1);
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/* 3. Perform 8 refresh cycles. Wait tRC each time. */
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PRINT_DEBUG("RAM Enable 3: CBR\r\n");
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do_ram_command(ctrl, RAM_COMMAND_CBR, 0, row_offset);
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do_ram_command(RAM_COMMAND_CBR, 0, row_offset);
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for (i = 0; i < 8; i++) {
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read32(0);
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read32(row_offset);
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@ -350,12 +341,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* 4. Mode register set. Wait two memory cycles. */
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PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
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do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0, row_offset);
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do_ram_command(RAM_COMMAND_MRS, 0x1d0, row_offset);
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udelay(2);
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/* 5. Normal operation (enables refresh) */
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PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
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do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0, row_offset);
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do_ram_command(RAM_COMMAND_NORMAL, 0, row_offset);
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udelay(1);
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PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
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@ -24,10 +24,8 @@
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/* The 82810 supports max. 2 dual-sided DIMMs. */
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#define DIMM_SOCKETS 2
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struct mem_controller {
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device_t d0;
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uint16_t channel0[DIMM_SOCKETS];
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};
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/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
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#define DIMM_SPD_BASE 0x50
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/* The following table has been bumped over to this header to avoid clutter in
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* raminit.c. It's used to translate the value read from SPD Byte 31 to a value
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