mb/intel/mtlrvp: Enable ACPI and add ACPI table
This enables ACPI configuration and add ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -1,6 +1,7 @@
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config BOARD_INTEL_MTLRVP_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select SOC_INTEL_METEORLAKE
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## SPDX-License-Identifier: GPL-2.0-or-later
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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subdirs-y += variants/$(VARIANT_DIR)
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@ -11,4 +11,18 @@ DefinitionBlock(
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/meteorlake/acpi/southbridge.asl>
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}
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#endif /* __BASEBOARD_GPIO_H__ */
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