diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h
index b29afa6892..c8a4c9b910 100755
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h
@@ -74,9 +74,6 @@
 //#define PCIE_LINK_GPIO_RESET_ASSERT_TIME       (2  * 1000)
 //#define PCIE_LINK_RESET_TO_TRAINING_TIME       (2  * 1000)
 
-#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1))
-#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
-
 // Get lowest PHY lane on engine
 #define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF)
 // Get highest PHY lane on engine
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h
index 1d80410b21..9941608b31 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h
@@ -66,8 +66,7 @@
 
 #define UNUSED_LANE_ID                         128
 
-#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1))
-#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
+#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==0))
 
 // Get lowest PHY lane on engine
 #define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF)
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
index 330a02e3d0..3821ac7110 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
@@ -263,12 +263,13 @@ PcieOnConfigureGppEnginesLaneAllocation (
   CoreLaneIndex = 0;
   PortIdIndex = 0;
   do {
+    if (PortIdIndex > 0) EnginesList++;
     EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
     EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++];
     EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
     EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
 
-  } while (IS_LAST_DESCRIPTOR (EnginesList++));
+  } while (IS_LAST_DESCRIPTOR (EnginesList));
   return  AGESA_SUCCESS;
 }
 
@@ -305,12 +306,13 @@ PcieOnConfigureDdiEnginesLaneAllocation (
   }
   LaneIndex = 0;
   do {
+    if (LaneIndex > 0) EnginesList++;
     EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
     EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
                                         Wrapper->StartPhyLane;
     EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
                                       Wrapper->StartPhyLane;
-  } while (IS_LAST_DESCRIPTOR (EnginesList++));
+  } while (IS_LAST_DESCRIPTOR (EnginesList));
   return  AGESA_SUCCESS;
 }