supermicro/h8qgi & h8scm: Remove a trailing whitespace
Change-Id: I9d44679f32b917dae42b9a6920c3d3c54626dcda Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6324 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -30,15 +30,15 @@
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* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
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* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
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*/
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*/
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/* MEMORY_BUS_SPEED */
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/* MEMORY_BUS_SPEED */
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#define DDR400_FREQUENCY 200 ///< DDR 400
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#define DDR400_FREQUENCY 200 ///< DDR 400
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#define DDR533_FREQUENCY 266 ///< DDR 533
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#define DDR533_FREQUENCY 266 ///< DDR 533
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#define DDR667_FREQUENCY 333 ///< DDR 667
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#define DDR667_FREQUENCY 333 ///< DDR 667
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#define DDR800_FREQUENCY 400 ///< DDR 800
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#define DDR800_FREQUENCY 400 ///< DDR 800
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#define DDR1066_FREQUENCY 533 ///< DDR 1066
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#define DDR1066_FREQUENCY 533 ///< DDR 1066
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#define DDR1333_FREQUENCY 667 ///< DDR 1333
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#define DDR1333_FREQUENCY 667 ///< DDR 1333
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#define DDR1600_FREQUENCY 800 ///< DDR 1600
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#define DDR1600_FREQUENCY 800 ///< DDR 1600
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#define DDR1866_FREQUENCY 933 ///< DDR 1866
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#define DDR1866_FREQUENCY 933 ///< DDR 1866
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#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
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#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
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/* QUANDRANK_TYPE*/
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/* QUANDRANK_TYPE*/
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#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
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#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
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@ -31,13 +31,13 @@
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* Enable check for PCIe endpoint to be ready for PCI enumeration.
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* Enable check for PCIe endpoint to be ready for PCI enumeration.
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*
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*
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*/
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*/
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//#define EPREADY_WORKAROUND_DISABLED
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//#define EPREADY_WORKAROUND_DISABLED
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/**
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/**
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* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
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* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
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*
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*
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*/
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*/
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#define IOMMU_SUPPORT_DISABLE //TODO: enable it
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#define IOMMU_SUPPORT_DISABLE //TODO: enable it
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/**
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/**
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* Disable server PCIe hotplug support.
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* Disable server PCIe hotplug support.
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@ -30,15 +30,15 @@
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* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
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* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
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*/
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*/
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/* MEMORY_BUS_SPEED */
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/* MEMORY_BUS_SPEED */
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#define DDR400_FREQUENCY 200 ///< DDR 400
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#define DDR400_FREQUENCY 200 ///< DDR 400
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#define DDR533_FREQUENCY 266 ///< DDR 533
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#define DDR533_FREQUENCY 266 ///< DDR 533
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#define DDR667_FREQUENCY 333 ///< DDR 667
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#define DDR667_FREQUENCY 333 ///< DDR 667
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#define DDR800_FREQUENCY 400 ///< DDR 800
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#define DDR800_FREQUENCY 400 ///< DDR 800
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#define DDR1066_FREQUENCY 533 ///< DDR 1066
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#define DDR1066_FREQUENCY 533 ///< DDR 1066
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#define DDR1333_FREQUENCY 667 ///< DDR 1333
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#define DDR1333_FREQUENCY 667 ///< DDR 1333
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#define DDR1600_FREQUENCY 800 ///< DDR 1600
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#define DDR1600_FREQUENCY 800 ///< DDR 1600
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#define DDR1866_FREQUENCY 933 ///< DDR 1866
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#define DDR1866_FREQUENCY 933 ///< DDR 1866
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#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
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#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
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/* QUANDRANK_TYPE */
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/* QUANDRANK_TYPE */
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#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
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#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
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@ -31,13 +31,13 @@
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* Enable check for PCIe endpoint to be ready for PCI enumeration.
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* Enable check for PCIe endpoint to be ready for PCI enumeration.
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*
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*
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*/
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*/
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//#define EPREADY_WORKAROUND_DISABLED
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//#define EPREADY_WORKAROUND_DISABLED
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/**
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/**
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* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
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* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
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*
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*
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*/
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*/
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#define IOMMU_SUPPORT_DISABLE //TODO: enable it
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#define IOMMU_SUPPORT_DISABLE //TODO: enable it
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/**
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/**
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* Disable server PCIe hotplug support.
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* Disable server PCIe hotplug support.
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