GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/skylake: Enable SA IMGU depending on devicetree configuration 

Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.

All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.

Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-07-29 22:28:37 +02:00 committed by Michael Niewöhner
parent 88264ef30b
commit 4d5c4e069c
12 changed files with 13 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
register "SaImguEnable" = "0"
register "Cio2Enable" = "0"
register "PmTimerDisabled" = "1"
register "HeciEnabled" = "0"
@ -239,6 +238,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # Thermal Subsystem
device pci 05.0 off end # SA IMGU
device pci 08.0 on end # Gaussian Mixture Model
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)

2
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -247,6 +246,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 on end # SA IMGU
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on
chip drivers/usb/acpi

2
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -267,6 +266,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem

2
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -282,6 +281,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 off end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem

2
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -288,6 +287,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem

2
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -267,6 +266,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 on end # SA IMGU
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""

2
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -246,6 +245,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 off end # SA IMGU
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""

2
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -268,6 +267,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem

2
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@ -10,7 +10,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "PmTimerDisabled" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
@ -121,6 +120,7 @@ chip soc/intel/skylake
}"
device domain 0 on
device pci 05.0 on end # SA IMGU
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3

2
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -45,7 +45,6 @@ chip soc/intel/skylake
register "HeciEnabled" = "1"
register "PmTimerDisabled" = "1"
register "SaGv" = "SaGv_Enabled"
register "SaImguEnable" = "0"
register "IslVrCmd" = "2"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "4" # 4s
@ -218,6 +217,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA thermal subsystem
device pci 05.0 off end # SA IMGU
device pci 08.0 off end # Gaussian Mixture Model
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on end # USB xHCI

4
src/soc/intel/skylake/chip.c
View File

@ -230,7 +230,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SerialIoDevMode));
params->PchCio2Enable = config->Cio2Enable;
params->SaImguEnable = config->SaImguEnable;
dev = pcidev_path_on_root(SA_DEVFN_IMGU);
params->SaImguEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev ? dev->enabled : 0;

1
src/soc/intel/skylake/chip.h
View File

@ -302,7 +302,6 @@ struct soc_intel_skylake_config {
/* Camera */
u8 Cio2Enable;
u8 SaImguEnable;
/* eMMC and SD */
u8 ScsEmmcHs400Enabled;