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southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitions 

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ia113672fa3cb740cb193c23fd06181d9ce895ac3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:25:50 -05:00
parent e99194555b
commit 4d7a9a5569
2 changed files with 3 additions and 7 deletions
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1
src/southbridge/intel/fsp_rangeley/Kconfig
View File

@ -21,6 +21,7 @@ if SOUTHBRIDGE_INTEL_FSP_RANGELEY
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG

9
src/southbridge/intel/fsp_rangeley/soc.h
View File

@ -18,6 +18,8 @@
#ifndef SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
#define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
#include <arch/acpi.h>
/* SOC types */
#define SOC_TYPE_RANGELEY 0x1F
@ -316,13 +318,6 @@ void rangeley_sb_early_initialization(void);
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP (7 << 10)
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)