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payloads/external/SeaBIOS: Allow setting buffers below 0xC0000 

Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is a requirement on the Intel Rangeley processor
because it is designed so that only the processor can write
the higher memory areas.  This prevents USB and SATA from bus-mastering
into the buffers when they're set in the typical 0xE0000 area.

This will be set to Y unless defaulted to N by the mainboard or
chipset.

Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak

Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth 2014-07-25 14:39:05 -06:00 committed by Martin Roth
parent b3997ba6f2
commit 4d7d25f38a
4 changed files with 25 additions and 0 deletions
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3
payloads/external/SeaBIOS/Makefile.inc vendored
View File

@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y)
else
echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config
endif
ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y)
echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config
endif
ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config
endif

13
src/Kconfig
View File

@ -623,6 +623,19 @@ config SEABIOS_THREAD_OPTIONROMS
variations during option ROM code execution. It is not
known if all option ROMs will behave properly with this option.
config SEABIOS_MALLOC_UPPERMEMORY
bool
default y
depends on PAYLOAD_SEABIOS
help
Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
"low memory" allocations. If this is not selected, the memory is
instead allocated from the "9-segment" (0x90000-0xa0000).
This is not typically needed, but may be required on some platforms
to allow USB and SATA buffers to be written correctly by the
hardware. In general, if this is desired, the option will be
set to 'N' by the chipset Kconfig.
choice
prompt "GRUB2 version"
default GRUB2_MASTER

1
src/arch/x86/Makefile.inc
View File

@ -351,6 +351,7 @@ seabios:
CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \
CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \
CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \
CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \
OUT=$(abspath $(obj)) IASL="$(IASL)"
filo:

8
src/mainboard/intel/mohonpeak/Kconfig
View File

@ -96,4 +96,12 @@ config UART_FOR_CONSOLE
help
The Mohon Peak board uses COM2 (2f8) for the serial console.
config SEABIOS_MALLOC_UPPERMEMORY
bool
default n
help
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment. This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.
endif # BOARD_INTEL_MOHONPEAK