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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-55 

Creator:  Yinghai Lu <yhlu@tyan.com>

intel car to x86 car


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical) 2005-07-06 17:23:57 +00:00
parent 54d6b08f01
commit 4d8620eecb
3 changed files with 10 additions and 10 deletions
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4
src/mainboard/tyan/s2735/Config.lb
View File

@ -101,7 +101,7 @@ if USE_DCACHE_RAM
end end
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/intel/car/cache_as_ram.lds ldscript /cpu/x86/car/cache_as_ram.lds
end end
end end
@ -133,7 +133,7 @@ if USE_DCACHE_RAM
## ##
## Setup Cache-As-Ram ## Setup Cache-As-Ram
## ##
mainboardinit cpu/intel/car/cache_as_ram.inc mainboardinit cpu/x86/car/cache_as_ram.inc
end end
### ###

6
src/mainboard/tyan/s2735/cache_as_ram_auto.c
View File

@ -80,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
#include "cpu/intel/car/copy_and_run.c" #include "cpu/x86/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
@ -295,11 +295,11 @@ cpu_reset_x:
if(cpu_reset==0) { if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1 #define CLEAR_FIRST_1M_RAM 1
#include "cpu/intel/car/cache_as_ram_post.c" #include "cpu/x86/car/cache_as_ram_post.c"
} }
else { else {
#undef CLEAR_FIRST_1M_RAM #undef CLEAR_FIRST_1M_RAM
#include "cpu/intel/car/cache_as_ram_post.c" #include "cpu/x86/car/cache_as_ram_post.c"
} }
__asm__ volatile ( __asm__ volatile (

10
src/mainboard/tyan/s2880/Config.lb
View File

@ -143,11 +143,11 @@ chip northbridge/amd/amdk8/root_complex
device pci 9.0 on end #broadcom device pci 9.0 on end #broadcom
device pci 9.1 on end device pci 9.1 on end
end end
chip drivers/lsi/53c1030 # chip drivers/lsi/53c1030
device pci a.0 on end # device pci a.0 on end
device pci a.1 on end # device pci a.1 on end
register "fw_address" = "0xfff8c000" # register "fw_address" = "0xfff8c000"
end # end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end