Rewrite interrupt handling in coreboot to be more comprehensible and
more flexible. Also some minore device allocator cleanups that sneaked in. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
c366cd0650
commit
4d933dd2d6
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@ -50,6 +50,10 @@
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#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
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#include <device/cardbus.h>
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#endif
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#define CONFIG_PC80_SYSTEM 1
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#if CONFIG_PC80_SYSTEM == 1
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#include <pc80/i8259.h>
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#endif
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u8 pci_moving_config8(struct device *dev, unsigned int reg)
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{
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@ -110,10 +114,10 @@ u32 pci_moving_config32(struct device * dev, unsigned int reg)
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unsigned pci_find_next_capability(struct device *dev, unsigned cap,
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unsigned last)
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{
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unsigned pos;
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unsigned pos = 0;
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unsigned status;
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unsigned reps = 48;
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pos = 0;
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status = pci_read_config16(dev, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST)) {
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return 0;
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@ -1193,86 +1197,62 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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return max;
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}
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#if CONFIG_PC80_SYSTEM == 1
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/**
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* Tell the EISA int controller this int must be level triggered.
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*
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* THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
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*/
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void pci_level_irq(unsigned char intNum)
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{
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unsigned short intBits = inb(0x4d0) | (((unsigned)inb(0x4d1)) << 8);
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printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
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intBits |= (1 << intNum);
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printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
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/* Write new values. */
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outb((unsigned char)intBits, 0x4d0);
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outb((unsigned char)(intBits >> 8), 0x4d1);
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/* This seems like an error but is not. */
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if (inb(0x4d0) != (intBits & 0xff)) {
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printk_err(
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"%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
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__func__, intBits & 0xff, inb(0x4d0));
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}
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if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
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printk_err(
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"%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
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__func__, (intBits >> 8) & 0xff, inb(0x4d1));
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}
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}
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/**
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* This function assigns IRQs for all functions contained within the
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* indicated device address. If the device does not exist or does not
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* require interrupts then this function has no effect.
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* @brief Assign IRQ numbers
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*
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* This function assigns IRQs for all functions contained within the indicated
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* device address. If the device does not exist or does not require interrupts
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* then this function has no effect.
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*
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* This function should be called for each PCI slot in your system.
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*
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* pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
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* this slot.
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*
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* The particular irq #s that are passed in depend on the routing inside
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* your southbridge and on your motherboard.
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*
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* -kevinh@ispiri.com
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*
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*/
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* @param bus
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* @param slot
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* @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through
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* PINTD of this slot. The particular irq #s that are passed in
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* depend on the routing inside your southbridge and on your
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* motherboard.
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*/
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void pci_assign_irqs(unsigned bus, unsigned slot,
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const unsigned char pIntAtoD[4])
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{
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unsigned functNum;
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struct device *pdev;
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unsigned char line;
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unsigned char irq;
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unsigned char readback;
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unsigned int funct;
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device_t pdev;
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u8 line;
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u8 irq;
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u8 readback;
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/* Each slot may contain up to eight functions. */
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for (functNum = 0; functNum < 8; functNum++) {
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pdev = dev_find_slot(bus, (slot << 3) + functNum);
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/* Each slot may contain up to eight functions */
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for (funct = 0; funct < 8; funct++) {
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pdev = dev_find_slot(bus, (slot << 3) + funct);
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if (!pdev)
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continue;
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if (pdev) {
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line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
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/* PCI spec says all other values are reserved. */
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if ((line >= 1) && (line <= 4)) {
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// PCI spec says all values except 1..4 are reserved.
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if ((line < 1) || (line > 4))
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continue;
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irq = pIntAtoD[line - 1];
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printk_debug("Assigning IRQ %d to %d:%x.%d\n",
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irq, bus, slot, functNum);
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irq, bus, slot, funct);
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pci_write_config8(pdev, PCI_INTERRUPT_LINE,
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pIntAtoD[line - 1]);
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readback =
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pci_read_config8(pdev, PCI_INTERRUPT_LINE);
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#ifdef PARANOID_IRQ_ASSIGNMENTS
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readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
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printk_debug(" Readback = %d\n", readback);
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#endif
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// Change to level triggered.
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pci_level_irq(pIntAtoD[line - 1]);
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}
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}
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// Change to level triggered
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i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);
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}
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}
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#endif
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@ -27,24 +27,24 @@
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static struct bus *get_pbus(device_t dev)
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{
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struct bus *pbus;
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struct bus *pbus = NULL;
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if (!dev)
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die("get_pbus: dev is NULL!\n");
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else
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pbus = dev->bus;
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while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
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if (pbus == pbus->dev->bus) {
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printk_alert("%s in endless loop looking for a parent "
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"bus with ops_pci_bus for %s, breaking out\n",
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"bus with ops_pci_bus for %s, breaking out.\n",
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__func__, dev_path(dev));
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break;
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}
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pbus = pbus->dev->bus;
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}
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if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) {
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printk_emerg("%s Cannot find pci bus operations\n", dev_path(dev));
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printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev));
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die("");
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}
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return pbus;
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@ -73,7 +73,7 @@ unsigned pci_find_capability(device_t dev, unsigned cap);
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struct resource *pci_get_resource(struct device *dev, unsigned long index);
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void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
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void pci_dev_init(struct device *dev);
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void pci_level_irq(unsigned char intNum);
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void pci_assign_irqs(unsigned bus, unsigned slot,
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const unsigned char pIntAtoD[4]);
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@ -22,4 +22,8 @@
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void setup_i8259(void);
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#define IRQ_LEVEL_TRIGGERED 1
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#define IRQ_EDGE_TRIGGERED 0
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void i8259_configure_irq_trigger(int int_num, int is_level_triggered);
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#endif /* PC80_I8259_H */
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167
src/pc80/i8259.c
167
src/pc80/i8259.c
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@ -1,42 +1,141 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <pc80/i8259.h>
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/* code taken from:
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!
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! setup.S Copyright (C) 1991, 1992 Linus Torvalds
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!
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! setup.s is responsible for getting the system data from the BIOS,
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! and putting them into the appropriate places in system memory.
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! both setup.s and system has been loaded by the bootblock.
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*/
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/* we're getting screwed again and again by this problem of the 8259.
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* so we're going to leave this lying around for inclusion into
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* crt0.S on an as-needed basis.
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! well, that went ok, I hope. Now we have to reprogram the interrupts :-(
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! we put them right after the intel-reserved hardware interrupts, at
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! int 0x20-0x2F. There they won't mess up anything. Sadly IBM really
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! messed this up with the original PC, and they haven't been able to
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! rectify it afterwards. Thus the bios puts interrupts at 0x08-0x0f,
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! which is used for the internal hardware interrupts as well. We just
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! have to reprogram the 8259's, and it isn't fun.
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*/
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#include <console/console.h>
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#define MASTER_PIC_ICW1 0x20
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#define SLAVE_PIC_ICW1 0xa0
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#define ICW_SELECT (1 << 4)
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#define OCW_SELECT (0 << 4)
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#define ADI (1 << 2)
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#define SNGL (1 << 1)
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#define IC4 (1 << 0)
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#define MASTER_PIC_ICW2 0x21
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#define SLAVE_PIC_ICW2 0xa1
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#define INT_VECTOR_MASTER 0x20
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#define IRQ0 0x00
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#define IRQ1 0x01
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#define INT_VECTOR_SLAVE 0x28
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#define IRQ8 0x00
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#define IRQ9 0x01
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#define MASTER_PIC_ICW3 0x21
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#define CASCADED_PIC (1 << 2)
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#define MASTER_PIC_ICW4 0x21
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#define SLAVE_PIC_ICW4 0xa1
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#define MICROPROCESSOR_MODE (1 << 0)
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#define SLAVE_PIC_ICW3 0xa1
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#define SLAVE_ID 0x02
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#define MASTER_PIC_OCW1 0x21
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#define SLAVE_PIC_OCW1 0xa1
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#define IRQ2 (1 << 2)
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#define ALL_IRQS 0xff
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#define ELCR1 0x4d0
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#define ELCR2 0x4d1
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void setup_i8259(void)
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{
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outb(0x11, 0x20); /*! initialization sequence to 8259A-1*/
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outb(0x11, 0xA0); /*! and to 8259A-2*/
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outb(0x20, 0x21); /*! start of hardware int's (0x20)*/
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outb(0x28, 0xA1); /*! start of hardware int's 2 (0x28)*/
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outb(0x04, 0x21); /*! 8259-1 is master*/
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outb(0x02, 0xA1); /*! 8259-2 is slave*/
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outb(0x01, 0x21); /*! 8086 mode for both*/
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outb(0x01, 0xA1);
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outb(0xFF, 0xA1); /*! mask off all interrupts for now*/
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outb(0xFB, 0x21); /*! mask all irq's but irq2 which is cascaded*/
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/* A write to ICW1 starts the Interrupt Controller Initialization
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* Sequence. This implicitly causes the following to happen:
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* - Interrupt Mask register is cleared
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* - Priority 7 is assigned to IRQ7 input
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* - Slave mode address is set to 7
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* - Special mask mode is cleared
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*
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* We send the initialization sequence to both the master and
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* slave i8259 controller.
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*/
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outb(ICW_SELECT|IC4, MASTER_PIC_ICW1);
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outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1);
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/* Now the interrupt controller expects us to write to ICW2. */
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outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2);
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outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2);
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/* Now the interrupt controller expects us to write to ICW3.
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*
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* The normal scenario is to set up cascading on IRQ2 on the master
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* i8259 and assign the slave ID 2 to the slave i8259.
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*/
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outb(CASCADED_PIC, MASTER_PIC_ICW3);
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outb(SLAVE_ID, SLAVE_PIC_ICW3);
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/* Now the interrupt controller expects us to write to ICW4.
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*
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* We switch both i8259 to microprocessor mode because they're
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* operating as part of an x86 architecture based chipset
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*/
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outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2);
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outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2);
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/* Now clear the interrupts through OCW1.
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* First we mask off all interrupts on the slave interrupt controller
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* then we mask off all interrupts but interrupt 2 on the master
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* controller. This way the cascading stays alife.
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*/
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outb(ALL_IRQS, SLAVE_PIC_OCW1);
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outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
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}
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/**
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* @brief Configure IRQ triggering in the i8259 compatible Interrupt Controller.
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*
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* Switch a certain interrupt to be level / edge triggered.
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*
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* @param int_num legacy interrupt number (3-7, 9-15)
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* @param is_level_triggered 1 for level triggered interrupt, 0 for edge
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* triggered interrupt
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*/
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void i8259_configure_irq_trigger(int int_num, int is_level_triggered)
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{
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u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
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printk_spew("%s: current interrupts are 0x%x\n", __func__, int_bits);
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if (is_level_triggered)
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int_bits |= (1 << int_num);
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else
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int_bits &= ~(1 << int_num);
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/* Write new values */
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printk_spew("%s: try to set interrupts 0x%x\n", __func__, int_bits);
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outb((u8)(int_bits & 0xff), ELCR1);
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outb((u8)(int_bits >> 8), ELCR2);
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#ifdef PARANOID_IRQ_TRIGGERS
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/* Try reading back the new values. This seems like an error but is not ... */
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if (inb(ELCR1) != (int_bits & 0xff)) {
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printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
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__func__, (int_bits & 0xff), inb(ELCR1));
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}
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if (inb(ELCR2) != (int_bits >> 8)) {
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printk_err("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
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__func__, (int_bits>>8), inb(ELCR2));
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}
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#endif
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}
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/*
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* I like the way Linus says it:
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! Well, that certainly wasn't fun :-(. Hopefully it works, and we don't
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! need no steenking BIOS anyway (except for the initial loading :-).
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*/
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